JPS6256040A - 遅延時間補償回路 - Google Patents

遅延時間補償回路

Info

Publication number
JPS6256040A
JPS6256040A JP60195623A JP19562385A JPS6256040A JP S6256040 A JPS6256040 A JP S6256040A JP 60195623 A JP60195623 A JP 60195623A JP 19562385 A JP19562385 A JP 19562385A JP S6256040 A JPS6256040 A JP S6256040A
Authority
JP
Japan
Prior art keywords
signal
data
output
signals
delay time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60195623A
Other languages
English (en)
Japanese (ja)
Other versions
JPH035100B2 (show.php
Inventor
Takashi Sakata
隆 坂田
Toshio Hanabatake
花畑　利男
Hisanobu Fujimoto
藤本　尚延
Tetsuo Murase
村勢　徹郎
Fumihiro Ikawa
伊川　史洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60195623A priority Critical patent/JPS6256040A/ja
Priority to DE19863688410 priority patent/DE3688410T2/de
Priority to EP19860112327 priority patent/EP0213641B1/en
Publication of JPS6256040A publication Critical patent/JPS6256040A/ja
Publication of JPH035100B2 publication Critical patent/JPH035100B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)
JP60195623A 1985-09-04 1985-09-04 遅延時間補償回路 Granted JPS6256040A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP60195623A JPS6256040A (ja) 1985-09-04 1985-09-04 遅延時間補償回路
DE19863688410 DE3688410T2 (de) 1985-09-04 1986-09-04 Verfahren, System und Schaltung zur Anpassung der Verzögerungszeit.
EP19860112327 EP0213641B1 (en) 1985-09-04 1986-09-04 Delay time adjusting method, circuit, and system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60195623A JPS6256040A (ja) 1985-09-04 1985-09-04 遅延時間補償回路

Publications (2)

Publication Number Publication Date
JPS6256040A true JPS6256040A (ja) 1987-03-11
JPH035100B2 JPH035100B2 (show.php) 1991-01-24

Family

ID=16344247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60195623A Granted JPS6256040A (ja) 1985-09-04 1985-09-04 遅延時間補償回路

Country Status (3)

Country Link
EP (1) EP0213641B1 (show.php)
JP (1) JPS6256040A (show.php)
DE (1) DE3688410T2 (show.php)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0446430A (ja) * 1990-06-14 1992-02-17 Fujitsu Ltd 位相補正方法及び回路
US5278651A (en) * 1990-05-28 1994-01-11 Fujitsu Limited Method and apparatus for synchronizing respective phases of high definition television signal components

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4979190A (en) * 1988-04-01 1990-12-18 Digital Equipment Corporation Method and apparatus for stabilized data transmission
US4811364A (en) * 1988-04-01 1989-03-07 Digital Equipment Corporation Method and apparatus for stabilized data transmission
US5119402A (en) * 1990-06-26 1992-06-02 Digital Equipment Corporation Method and apparatus for transmission of local area network signals over unshielded twisted pairs
US5341405A (en) * 1991-06-11 1994-08-23 Digital Equipment Corporation Data recovery apparatus and methods
US5408473A (en) * 1992-03-03 1995-04-18 Digital Equipment Corporation Method and apparatus for transmission of communication signals over two parallel channels
CA2140533C (en) * 1992-07-20 2004-11-23 Roland Bruckner Method for forwarding a message cell stream via a plurality of parallel trunks while adhering to the sequence of the message cells
US5359630A (en) * 1992-08-13 1994-10-25 Digital Equipment Corporation Method and apparatus for realignment of synchronous data
US6336192B1 (en) * 1998-02-16 2002-01-01 Nippon Telegraph And Telephone Corporation Parallel redundancy encoding apparatus
EP0996262A1 (en) 1998-10-22 2000-04-26 Texas Instruments France Communication system with plurality of synchronised data links
US6963989B1 (en) * 2000-05-22 2005-11-08 Micron Technology, Inc. Method and apparatus for adjusting data hold timing of an output circuit
US7035368B2 (en) 2002-03-18 2006-04-25 Texas Instruments Incorporated High speed parallel link receiver

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB968730A (show.php) * 1962-02-09

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278651A (en) * 1990-05-28 1994-01-11 Fujitsu Limited Method and apparatus for synchronizing respective phases of high definition television signal components
JPH0446430A (ja) * 1990-06-14 1992-02-17 Fujitsu Ltd 位相補正方法及び回路

Also Published As

Publication number Publication date
DE3688410T2 (de) 1993-11-11
EP0213641A2 (en) 1987-03-11
EP0213641B1 (en) 1993-05-12
DE3688410D1 (de) 1993-06-17
EP0213641A3 (en) 1989-05-03
JPH035100B2 (show.php) 1991-01-24

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