JPS6256040A - Delay time compensation circuit - Google Patents

Abstract

PURPOSE:To absorb the delay time difference of the 1st and 2nd signals by reading sequentially a bit corresponding to the 1st elastic memory in response to an output of a ring counter having the same bit number as that of the 1st and 2nd elastic memories. CONSTITUTION:The 2nd data signal B and the 2nd synchronizing signal B are subject to a prescribed bit number of delay respectively by a fixed delay circuit. On the other hand, the 1st data signal A and the 1st synchronizing signal A are written respectively in the 1st and 2nd elastic memories 101, 102 at the same time and a data corresponding to the 1st elastic memory 101 is read sequentially via a data selector 105 in response to the output of a counter 104 into which the location of the 1st synchronizing signal A in the 2nd elastic memory 102 is loaded by the synchronizing signal B delayed by a fixed delay circuit 103. Thus, the output of the 1st data signal A adjusted for the delay time difference with the 2nd data signal B is obtained at the output of the data selector 105.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Actions Embodiments Effects of the Invention C Overview] Multiple high-speed data signals A second signal and a second synchronization signal synchronized with the second signal are used on the receiving side of a signal transmission method in which the signals are divided into low-speed data signals and transmitted through different transmission paths, and the receiving side absorbs the delay time difference between the two signals. A first signal and a first synchronization signal synchronized therewith are operated in conjunction with the clock of the first signal, and the first and second errors have the same bit length. write to the stick memory simultaneously and write the second elastic in response to a delayed second synchronization signal.
The position of the first synchronization signal in the memory is changed according to the output of a ring color having the same number of bits as the first and second elastic memories operated by the clock of the first signal loaded. Since the corresponding bits of the elastic memory are sequentially read out, it is possible to obtain the first signal output in which the delay time difference with the second signal is completely absorbed.

[Industrial application field]

The present invention relates to a signal transmission system, and more particularly to a delay time compensation circuit that uses an elastic memory to absorb a delay time difference between two signals that are transmitted separately.

Due to the capacity of the transmission line, it may be necessary to divide a single high-speed signal into multiple low-speed signals for transmission, and then combine them into a single high-speed signal on the receiving side for reception. is.

FIG. 5 shows an example of the configuration in such a case, in which the transmitting device 1 converts, for example, a PAL image signal into a Dpcu (differential pcu) and transmits it at 6sMb/see.
This signal is divided into two low-speed signals A and B through the distribution device 2, and both signals A and E'E are respectively CCIT.
The signal is transmitted through the transmission lines 5 and 4 having a speed of 54.568 Wb/age specified in the T recommendation, and the combiner 5 combines both signals to generate a signal of 68 Mb/sea again, and the receiver device 6 This is received at . At this time, in order for both signals to be correctly combined on the receiving side, it is necessary that the propagation delay times of both signals be equal, but in reality, propagation delay time differences occur due to various causes.

The main factors that cause such a propagation delay time difference are a signal propagation time difference in the transmission path itself and a delay in an elastic memory in a stack multiplexer when multiplexing transmission signals.

The signal propagation time of the transmission line itself is 89 per 1 mu of the transmission line, which is 5 sage for 54.568 Mb/sea.
X 34.368. M6/ago = 171.8
Corresponds to bit. Therefore, if we assume that errors in transmission line length, differences in propagation characteristics, delay time differences due to temperature fluctuations, etc. are totaled and a difference of 10 inches is expected, a relative difference of 17.26 it can occur between the image transmission lines. .

Also, the above-mentioned s4. 159.264 Mb/s by multiplexing 4 s6sMb/sea signals and adding stuff pulses
When a transmission line includes a multiplexer that creates a go signal, the transmitting side and the r-mail address are usually
It has an IO/(ft) memory, and the delay time in this part fluctuates between 0 and 20 bits.

Therefore, in order to combine these signals and combine the signals of the two transmission paths on the receiving side, a total time difference of *572 bits must be absorbed.

The present invention is intended to provide a means for absorbing delay time differences that is effective in such cases.

[Conventional technology]

As a means for absorbing the delay time difference between two signals, a method has been used in the past in which an elastic memory is inserted into one transmission path to delay one signal.

FIG. 6 shows the configuration of a conventional elastic memory, illustrating a case of 6 bits.
11 is required for the 5-bit S/G circuit, and 12 is required for the S/D circuit. 1! 14 and 15 are respectively flip-flops (hereinafter abbreviated as FF), which are 3-bit memory cells made of gold, 16 is a 3-pin ring counter, and 17 is a 3-pin ring counter. 18 is a data selector, and 19 is a phase comparator.

Moreover, FIG. 7 shows the signals of each part in the elastic memory shown in FIG.
6's Q1 output.

In FIG. 6, the ring counter 11 has a write clock B synchronized with the data input applied to the clock terminal CK, and outputs Q1. The NAND operation output of Q2 is connected to the signal input terminal S,
By being applied to IN, the output that becomes “1” sequentially at each rising edge of the write clock is output to terminals Q+, Qz, and Qs.
occurs in The ring color/receiver 16 also performs a similar operation using the read clock A.

F-F15°F-F forming a 3-bit memory cell
14, F-F 15 K is data input (+$+
6+ 41+ d+ at...) are added to the data terminals in parallel.

F-F13 is the clock terminal CK input counter 11
By adding the Q1 output of
...) occurs.

The data selector 18 selects the output ■ of the F-F 15 every time the output ■ of the ring counter 16 rises, and produces data outputs (a, d, . . . ). Similarly
Data output (b, g+・
・Tsu.

(i...) is produced. Therefore, in the elastic memory shown in FIG. 6, each of the seven lip-flops is read out at a maximum interval of five pits using the read clock, so that data input can be output with a delay of 0 to 3 bits. At this time, the phase comparator 19 has both ring counters 11
．． By comparing the Q of L6 and the phase of the output, a phase difference output indicating the phase difference between the data input and data output is generated.

In this case, read clock A has a somewhat faster speed than write clock B. Therefore, the phase of data output gradually advances, but
By thinning out the read clock A in a control section (not shown) using the phase difference output, the delay time difference between the data B output and the input is maintained at a desired value.

[Problem that the invention seeks to solve]

In the conventional elastic memory shown in FIG. 6, data on one transmission line can be delayed by a range of 0 to 3 bits with respect to a signal on the other transmission line. However, there was a problem that it was impossible to proceed.

[Means for solving problems]

FIG. 1 is a diagram showing the basic configuration of the present invention.

101 and 102 are first and second elastic
The memories 106 are of color, each having the same bit length, each receiving a first data signal A and a synchronization signal A synchronized therewith, and a clock A synchronized with the data signal A. It operates in conjunction with the output of the counter 106 that counts .

A fixed delay circuit 103 delays the second data signal B and the synchronization signal B synchronized therewith by the same number of bits.

104 is a counter which has the same number of bits as the first and second elastic memories 101 and 102, operates based on the clock B of the second data signal B, and receives the delayed second synchronization signal B. Second elastic according to
The location of the first synchronization signal A in memory 102 is loaded.

A data selector 105 sequentially reads corresponding data signals Af from the first elastic memory according to the output of the counter 104.

[Effect]

The second data signal B and the second synchronization signal B are each delayed by a fixed number of bits by a fixed delay circuit.

On the other hand, the first data signal A and the first synchronization signal A are transmitted to the first and M2 stick memories 101, respectively.
According to the output of the counter 104 loaded with the position of the first synchronization signal A in the second elastic memory 102, the synchronization signal B is simultaneously written to the first elastic memory 102 but delayed by the fixed delay circuit 103. , the first elastic memory 1 via the data selector 105
Since the data corresponding to 01 is read out sequentially, the first data signal A(2) output whose delay time difference with the second data signal B has been adjusted can be obtained as the output of the data selector 105.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the present invention, and the same parts as in FIG. 6 are designated by the same numbers.
1, 22, and 23 are respectively Furiragu and 70 Tsubu (hereinafter F
-F), which forms a 5-bit memory cell. Further, 24 is a fixed delay circuit. In the figure, one of the two data inputs A and B is given a fixed delay of 1.5 bits by the fixed delay circuit 24, and the other data input B is given a variable delay through a 3-bit elastic memory. In this example, synchronization signals A and E are signals indicating the same phase positions on the transmitting side of data inputs A and H, respectively.

FIG. 5 shows signals of various parts in the embodiment of FIG. 2. In the same figure, ■ indicates the input of writing tarokk B, ■, ■
, ■ are the respective Ql of the 5-bit ring counter 11.
, Q2 , Qs output, ■ is data B input, ■, 0. ■
are F-F 13, F-F1 and F-pis Q outputs, ■ are three synchronizing signals ■, [F], and ■ are F-F 21, F-F 22, F-F 23, respectively.
Q output, [phase] is successive clock A input, ■, ■, ■ are respectively Q+ of 5-bit ring counter 16,
Q2, Qs output buha ■ is the fixed delay circuit 241Z) synchronization signal output, ■ is the synchronization signal for four people, and ■ is required by the data B output of the data selector 18.

The ring color/receiver 11 outputs three-phase clock outputs ■, ■, ■ which become "1" sequentially at each rising edge by the write clock B synchronized with the data B input shown in ■. occurs at output terminals Q+, Q2, and Qs. On the other hand, F-F13 and F-F14 forming the memory cell
, F-F 15 has data B input (1, 2) shown in ■.
, 3, ...) are applied in parallel to each data terminal, and clocks ■, ■, ■ are applied to each clock terminal CK, respectively, and the data B input can be read at the rising edge of the clock. Accordingly, the output ■(1, 4, ...), ■(2,
5°°°・), ■(3, 6,...) is produced.

In addition, the synchronization signal B input shown in ■ is F-F21, F-
F22.

The clocks 1, 2, and 2 are applied in parallel to the data terminals of the F-F 23, and clocks 1, 2, and 2 are applied to the respective clock terminals CK, and the synchronizing signal B is read at the rising edge of the clocks. The synchronization signal B is synchronized with the signal (1) at the data B input, and the 3-bit period from when 1" is read into F-F 22 by the rising edge of the clock ■ until the next rising edge of the clock ■. , its output ■ holds "1". On the other hand, outputs ■ and ■ remain "0".

On the other hand, the data A input and the synchronization signal A input shown at @ are delayed by 1.5 bits in the fixed delay circuit 24 to produce the data A output and the synchronization signal output ■. The 3-bit ring counter 16 connects the synchronization signal output ■ to the load terminal LO.
When the signal applied to AD is “1”, the rising edge of the clock A input @ causes the data terminal to
+ D2 + Output added to DS ■, ■, ■
are loaded with the values of and produce the outputs ■, ■, and ■, respectively. In other words, at this time, the output @ is “1”, the output ■, ■
is "0".

When the output ■ becomes "1", the data selector 18 selects and outputs the data ■ of the corresponding F-F1a, and thereby the data (1) is output to the data B output shown in ■. . 3-bit ring color/re16 is [
The read clock A input shown in
The outputs ■, ■, ■, which are given to terminals Q1 and 1 and become "1" sequentially at each rising edge, are respectively connected to terminals Q1. Occurs on ch, Qs. The data selector 18 sequentially selects the corresponding data according to the outputs ■, ■, ■.

■ Select and output. As a result, data B shown in ■
Thereafter, the data (21, f31, (4), . . . ) are sequentially selected and output as the output.

In this way, the synchronization signal A(
@), data B is set to data selector 1.
8 and is output to its output (2), and the phase difference between both data A and E is adjusted.

According to the next embodiment shown in FIG. 2, when the data A input has a phase difference in the range of ±1.5 bits compared to the data B input, this can be adjusted to match the phases.

In FIG. 3, ■ indicates when the data A input has advanced by 1.5 bits compared to the data B input, and ■ indicates the same <1.
This shows when you are 5 pits behind. In this case, the synchronizing signal A (■) passing through the fixed delay circuit 24 is also 1.
Since the output is advanced or delayed by 5 bits, the data B output shown in (3) is also advanced or delayed by the same amount, and the phase adjustment is performed in the same way for the data A output.

FIG. 4 shows an example of application of the method of the present invention to an actual device. In the figure, a case is illustrated in which the phase of multiplexed third-order group data D30 inputs 1 and 2 having a phase difference of ±D bits is adjusted, and the first input D3 INl consisting of a bipolar signal is , a bipolar-unipolar conversion circuit (E/U) 31, the signal is converted into a unipolar signal, and then the HDE3 decoding circuit (HDB 3/U)
The high-density bipolar (HDB5) code is decoded at 52, which is the same as the 54Mb/aao data signal (34
Mb/sea clock signal is generated. Separation circuit (D
MUX) 33 demultiplexes these signals to 4Mb
8 data signals of /sec and a clock signal and frame signal of 4M6/8## are generated. The eight data signals and frame signals are delayed through nine 8-bit delay circuits in the fixed delay circuit 54, and the data signals are output as output data DATAOUT1.

On the other hand, the second data input D5 1N2 is also a bipolar-unipolar conversion circuit (B/v) 35, 1DB
Eight data signals of 4 Mb/1g6 and a clock signal and frame signal of 4 Mb/H6 are generated through the sffl encoding circuit (Hns3/v) s6 and the separation circuit (nuvX) 67. The eight data signals and frame signals are input to a variable delay circuit 38 and delayed through nine Hirobit delay circuits. The variable delay circuit 58 is according to the present invention, uses the clock signal of the separation circuit 5704Mk/age as a write clock, and uses the clock signal of the separation circuit 56 as a write clock.
y.

The fixed delay circuit 3 uses the clock signal as the read clock.
4 as a delayed synchronization signal for loading, and operates in the same manner as the embodiment shown in FIG. .

〔Effect of the invention〕

As explained above, according to the signal transmission method of the present invention, one signal is added to the elastic memory and the signal is incremented by the number of bits corresponding to the delay time difference between the synchronization signals of the two signals. The elastic memory is read by the output to obtain the output, and the other signal is given a certain fixed delay, so whether one signal lags or leads the other signal, there is no difference between the two signals. can absorb the delay time difference.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a diagram showing the configuration of an embodiment of the invention, Fig. 3 is a diagram showing various signals in the embodiment of Fig. 2, and Fig. 4 is a diagram showing the configuration of an embodiment of the invention. 5 is a diagram showing an example of the configuration of a signal transmission system to which the method of the present invention is applied. FIG. 6 is a diagram showing the configuration of a conventional elastic memory. 7 is a diagram showing signals of each part in FIG. 6. 11, 16...Ring color/ri, 13, 14.15.21.22.23...7 lip
Flop, 12, 17... NAND circuit, 18... Data selector, 24... Fixed delay circuit

Claims (1)

[Claims] Delay time in a signal transmission method in which a high-speed data signal is divided into two low-speed data signals, each of which is transmitted via a different transmission path, and the delay time difference between the two signals is absorbed and combined on the receiving side. In the compensation circuit, the first signal and the synchronization signal synchronized therewith are connected to the first signal having the same bit length and operating in conjunction with the clock of the first signal.
and second elastic memory (101, 102
) at the same time, a fixed delay circuit (103) applies the same time delay to the second signal and a synchronization signal synchronized therewith, and the second elastic - Load the position of the first synchronization signal in the memory into a counter (104) having the same number of bits as the first and second elastic memories operated by the clock of the second signal, and according to the output of the counter. By sequentially reading out corresponding bits of the first elastic memory via a data selector (105), a first signal output in which a delay time difference with the second signal is absorbed is obtained. delay time compensation circuit.