CA2020607A1 - Circuit arrangement for word-by-word serial-to-parallel conversion - Google Patents
Circuit arrangement for word-by-word serial-to-parallel conversionInfo
- Publication number
- CA2020607A1 CA2020607A1 CA 2020607 CA2020607A CA2020607A1 CA 2020607 A1 CA2020607 A1 CA 2020607A1 CA 2020607 CA2020607 CA 2020607 CA 2020607 A CA2020607 A CA 2020607A CA 2020607 A1 CA2020607 A1 CA 2020607A1
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- CA
- Canada
- Prior art keywords
- bit
- serial
- word
- parallel
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
- H04J3/0608—Detectors therefor, e.g. correlators, state machines
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
In a circuit arrangement which converts a serial input bit sequence consisting of successive n-bit words to a parallel word format, a serial-to-parallel converter operates in an unsynchronized manner, i.e., with an arbitrary synchronization offset with respect to the word beginnings in the input bit sequence. A synchronizing circuit detects the offset of the synchronization and provides an offset signal. There is connected in series with the converter a circuit which, in accordance with the offset signal, rearranges the bit groups delivered by the serial-to-parallel converter in such a way that complete words are delivered successively to n outputs of the circuit arrangement. Instead of a synchronizing control circuit for the serial-to-parallel converter, a control circuit connected in series with the converter is used.
In a circuit arrangement which converts a serial input bit sequence consisting of successive n-bit words to a parallel word format, a serial-to-parallel converter operates in an unsynchronized manner, i.e., with an arbitrary synchronization offset with respect to the word beginnings in the input bit sequence. A synchronizing circuit detects the offset of the synchronization and provides an offset signal. There is connected in series with the converter a circuit which, in accordance with the offset signal, rearranges the bit groups delivered by the serial-to-parallel converter in such a way that complete words are delivered successively to n outputs of the circuit arrangement. Instead of a synchronizing control circuit for the serial-to-parallel converter, a control circuit connected in series with the converter is used.
Description
2~2~ ~7 CIRCUIT ARRANGEMENT FOR WORD-BY-WORD
SERIAL-TO-PARALLEL CONVERSION
BACKGROUND OF THE INVENTION
Field of the Invention The present invention relates to a circuit arrangement which converts a bit sequence consisting of successive n-bit words from serial to parallel form in a word-by-word manner .'.~. - - .
Description of the Prior Art ~ , A circuit arrangement of this general type is known, for example, from German Patent DE-Al 35 01 674 The circuit arrangement shown therein, in addition to a .. ' serial-to-parallel converter, contains a synchronizing circuit .:, .
which synchronizes the serial-to-parallel converter so that it ~ ~;
converts its input bit sequ:ence consisting of successive n-bit words-from serial to parall-l in a word-by-word manner, i e , in `~
~ . .
ach case~delivering a complete word at its parallel outputs On the basis of the words delivered by the serial-to-parallel converter, the synchronizing'circuit checks a code rule tolwhich ~. :
20~S0~ :
the successively received n-bit words are subject, and shifts the operating clock phase of the serial-to-parallel converter, for example, by one clock pulse period of the bit clock of the input bit sequence, possibly several times in sequence, until it no longer finds any code errors in the n-bit bit groups delivered by the serial-to-parallel converter, which means that these bit groups are actually the n-bit words The known arrangement thus synchronizes its serial-to-j ,, parallel converter by means of a control loop In a control of this type, subcircuits typically retroact on subcircuits connected in series with them This is particularly disadvantageous if the co-operating subcircuits are to be realized in different semiconductor technologies, depending upon . .
the speed of th- processing taking place in them In particular, it must be taken into consideration in this case that, in new oommunicatlon syste~s, the bit sequence frequencies of th- bit s-quences that are to be transmitted serially will be betwe-n 150 and 600 Mbit/s or even higher, and will thus require a relatively expensive T$L or ECL technology On the other hand, it is - 2~0~7 desirable, for cost reasons, to be able to use the CMOS
technology.
SUMMARY OF THE INVENTION
It is therefore the task of the invention to provide a circuit arrangement of the type mentioned above, which makes possible a realization of different subcircuits in different technologies to a greater extent than the known circuit arrangement.
The task is accomplished by a cirouit arrangement which converts a serial input bit sequence consisting of successive n-bit words to a parallel word format, a serial-to-parallel converter operates in an unsynchronized manner, i.e., with an arbitrary synchronization o~fset with respect to the word beginnings in the input bit sequence. A synchronizing circuit detects~the off et signal of the synchronization and provides an offset signal. There is connected in series with the converter a ~ -~
circuit whi¢h, in adcordande with the offset signal, rearranges bit groups~delivered by the serial-to-parallel converter in such `~
: ~ .
2 ~ 7 a way that complete words are delivered successively to n outputs of the circuit arrangement. Instead of a synchronizing circuit for the serial-to-parallel converter, a control circuit connected in series with the converter is used.
A circuit arrangement which converts a bit sequence, consisting of successive n-bit words, word by word from serial to parallel form, is characterized in that it contains a serial-to-parallel converter which converts the input bit sequence into n-bit bit groups with an arbitrary clock phase; a synchronizing -.,:
circuit which detects the word boundaries of the input bit sequence and, by comparing the word boundaries with the clock phase of the serial-to-parallel converter, produces a control signal indicating the synchronization offset of the serial-to-parallel converter; and a circuit which rearranges the n-bit bit groups from the serial-to-parallel converter word by word, and ~ `
delivers the n-bit words contained therein in parallel form under control of the control signal.
.`.
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~ ~ ~4---`` 2~2~7 DESCRIPTION OF THE DRAWING
, ~. ..
The drawing shows a block diagram of the circuit arrangement according to the invention in the upper part and the bit groups appearing successively at different points of the circuit arrangement in the lower part.
. .
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
. ;~
At an input of the circuit arrangement shown in the drawing ~ -there is provided a bit sequence in serial form with a specific -~
bit clock rate, e.g., lS0 Mbit/s. This bit sequence contains succesoive words with n, for example, 8 bits each. The circuit arrangement has the task of converting this bit sequence from serial to parallel in a word-by-word manner, i.e., in such a way that, at n outputs, the bits of a first word, and then those of a second word, etc., will appear successively, in each case in parallel form. For the following example, we shall always start from the fact that n'i~ eq~ai to 8.
~ . . . .
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--.
.
2~2~07 `
The circuit arrangement contains a serial-to-parallel converter 1, into which the input bit sequence is inputted serially. A circuit for clock derivation (not shown) derives the bit clock from the input bit sequence and divides this by 8 with an arbitrary phase. The serial-to-parallel converter 1 is operated with this bit clock divided by 8 as the operating clock signal. The operating clock signal is designated as OC in the ~
drawing. The serial-to-parallel converter 1 thus converts its ~;
input bit sequence into 8-bit bit groups, which it delivers ~ i~
successively in parallel form at its eight outputs, at the clock rate of the operating clock.
Since the phase of the operating clock, OC, of the serial-to- ;
parallel converter 1 is fixed, but arbitrary, and is not synchronized with the phase of the word boundaries of the words -;
oontained in the input bit sequence, the serial-to-parallel converter 1 generally operates with a synchronization delay, so that the n-blt bit groups delivered by it at the output are not ld-ntical to the n-bit words contained successively in the input bit sequence but contain bi'ts of different words.
, -6- ~
:~
.- ~
~ 2~2~7 The drawing shows this in an example, in which several bit groups B1, B2, B3 delivered successively by the serial-to-parallel converter 1 are in each case shown as eight connected boxes representing eight bits and the bits belonging to a word are in each case symbolized by a specific pattern. In the example shown, a first bit group Bl contains two bits (empty boxes) which are received as the last bits of a word W1, and six bits (diagonally dashed boxes) of a successively received word W2. The remaining two bits of W2 are contained in a bit group ~;:
B2, which appears one operating clock period later at the outputs of the serial-to-parallel converter 1 and which contains the first six bits of a word W3 (checkered boxes) as additional bits. The two remaining bits of the word W3 are contained in a. . i bit group B3, which again appears an operating clock period later (checkered boxes), and which contains the first six bits (dark - ~ -boxes) of a next word W4 as additional bits. The points in time at which these bit groups appear at the outputs of the serial-to-parallel converter 1 are indicated by t1, t2 and t3. As already -~ ~
mentioned, they areiseparated by one clock-pulse period of the -;
; operating clock, OC, of the serial-to parallel converter 1. ::' ~
:
2~007 In this example, therefore, the synchronization delay has a value of 2 bit clock-pulse periods. (If the phase of the operating clock were two bit clock-pulse periods earlier, then the bit groups Bl through B3 would each contain a complete word.) According to the invention, the serial-to-parallel converter -~
is not synchronized with the word boundaries of the input bit sequence (in contrast to the known arrangement mentioned in the Description of the Prior Art), but retains its synchronization ;~
delay, which can amount to 1-7 bits, and in series with the converter there is connected a circuit which, under the control of synchronization delay, makes certain that the bits contained ; ~;
in the input bit sequence are delivered word-by-word in parallel form.
A synchronizing circuit 2 for detection of the synchronization delay is provided. This circuit receives the , ~ operating clock, OC, of the serial-to-parallel converter and the ~ , ..
input bit sequence. In a manner that is of no interest to the prèsent invention, the circuit detects the word boundaries of the successivè n-bit wdrds,in the input bit sequence, compares the phase of a clock derived from the word boundaries with the phase ~ i ' :~
2~2~7 of the operating clock, and determines the phase delay of the operating clock relative to the phase of the word boundaries as, for example, two-bit delay period shown in the drawing. The synchronizing circuit accordingly delivers an eight-bit control signal S at its output indicating the synchronization delay.
The circuit controlled by this control signal could be any -memory circuit, into which the n-bit bit groups, such as Bl -through B3, etc., delivered successively by the serial-to-parallel converter 1 are inputted for interim storage and, controlled in accordance with the synchronization delay, are - -~
delivered in such a way that eight bits of a single word appear in parallel form at the eight parallel outputs. ~ `t As an advantageous embodiment of the invention, instead of a ~ ~`
memory of this type, a simpler circuit is used, as shown in the drawi~ng. This circuit rearranges the 8-bit bit groups B1, B2, ~ ;
B3, etc., delivered successively by the serial-to-parallel conv-rter in such a way that complete words are delivered successively in parallel form. The circuit contains a delay circuit 3, which deliays each of the bit groups~Bi deliverèd ~ succ-ssively by the serial-to-parallel converter by one clock-:~ ;: _g_ ~ .
: ~ ,.
2~"~7 pulse period of the operating clock, OC. The delay circuit 3 has eight parallel outputs provided to lines 6. A bus 4 having eight parallel lines is connected to the output of the serial-to- - i parallel converter and makes available each bit group Bi delivered by the serial-to-parallel converter 1 without delay and in parallel form. A selection circuit 5 receives 16 bits from lines 6 and bus 4 and delivers a specific eight bits of each 16-bit group, as will be explained below.
The action of this circuit is illustrated in the drawing and is easily understandable. A portion of the circuit consisting of ~ ~.
the delay circuit 3, bus 4 and lines 6, form two bit groups delivered successively by the serial-to-parallel converter 1.
The circuit portion in each case forms a word with twice the bit count (i.e., 16 bits) by adding the bits of a second bit group in parallel to a first bit group.
For example, at a time t2 a 16-bit bit group BB2 i9 formed.
This contains, side by side, the bits of a bit group Bl, which -~
was delivered by the series-to-parallel converter 1 one clock-pulse period of the operating clock earlier, and the bits!of the bit group B2 delivered at the time t2. In the same manner, there : .
~ -10-~`~
-- 2 ~
was formed at a time t1 a bit group BBl, which is composed of the bits of a bit group Bo appearing one clock-pulse period earlier and the bits of the bit group B1 appearing at the time tl. The earlier formed bit groups appear above the dashed line as the output bits of the delay circuit 3, and the later bits appear below the dashed line as the output bits of the serial-to-parallel converter 1, which are delivered undelayed by the bus 4. Also, a bit group BB3, composed of the bit groups B2 and B3, appears at a later time t3.
A seen in the drawing, all of these 16-bit groups BBi have the property that they contain a complete word, whose bits are located side by side, and that this word is in the same bit positions in all bit groups, for example, in the positions 3 to ~ "~
10, counting from top to bottom.
;~ ~The subsequent selection circuit S must now only switch through~to its eight outputs those eight of its 16 input lines that~contain the bits of a complete word in parallel form. In the~example shown, these are lines 3-10, if all of the lines are numbered with the numbers i-16 from top to bottom. If thése ::
lines are switched through to the outputs, then the words Wl, W2, :: :
~ : -11-: ~ ::: :
2 ~ 2 ~
W3, which are contained in the above-mentioned bit positions in the bit groups BB1, BB2, BB3, appear successively at the times tl, t2, t3 etc~
The selection circuit 5 is a central gate matrix for ~;
switching through n of 2n input lines to n output lines. This is a 2n x n gate matrix with 2n signal inputs and n control inputs, -into whose control inputs a control word S is inputted into n ~ - , .
control inputs by means of a bus line n bits in width. In the example shown, this is a control word which, for example, has a 1 in the third bit position and a O in all other bit positions, and the gate matrix operates in such a way that, when this word is applied to its control inputs, it connects its input lines 3-10 with its eight output lines.
Aslde from slight gate delays, the gate matrix does not cause any delay of the words to be delivered, and, overall, the cirauit has the advantage that, immediately after the synchronizing circuit 2 has detected the synchronization offset, it delivers the successive words in the correct order. The delay byione period of the operating clock, OC, that a part of a word undergoes until the remaining part of the word is available, has ~-- 2 0 ~ 7 no harmful effect on the further processing of the parallellized words. The synchronizing circuit 2 uses a simple logic circuit for generation of the control signal S. In the example shown, for a synchronization offset of two bits, the circuit 2 delivers an 8-bit word which has a 1 in the third bit position and only 0- ~ ;~
bits otherwise.
The part of the synchronizing circuit that detects the word boundaries in the input bit sequence can be a Xnown circuit, such as is generally used for word synchronization, e.g., a circuit that detects a frame synchronous word in the input bit sequence, as a result of which the word boundaries of the words transmitted in the frame are fixed.
It is not an absolute requirement that the synchronizing clrcuit 2 receive the bit sequence in serial form as an input signal. A synchronizing circuit can be used that evaluates the sequence of n-bit bit groups delivered by the serial-to-parallel converter 1 and can find the word boundaries in a parallel format.
~ -13-
SERIAL-TO-PARALLEL CONVERSION
BACKGROUND OF THE INVENTION
Field of the Invention The present invention relates to a circuit arrangement which converts a bit sequence consisting of successive n-bit words from serial to parallel form in a word-by-word manner .'.~. - - .
Description of the Prior Art ~ , A circuit arrangement of this general type is known, for example, from German Patent DE-Al 35 01 674 The circuit arrangement shown therein, in addition to a .. ' serial-to-parallel converter, contains a synchronizing circuit .:, .
which synchronizes the serial-to-parallel converter so that it ~ ~;
converts its input bit sequ:ence consisting of successive n-bit words-from serial to parall-l in a word-by-word manner, i e , in `~
~ . .
ach case~delivering a complete word at its parallel outputs On the basis of the words delivered by the serial-to-parallel converter, the synchronizing'circuit checks a code rule tolwhich ~. :
20~S0~ :
the successively received n-bit words are subject, and shifts the operating clock phase of the serial-to-parallel converter, for example, by one clock pulse period of the bit clock of the input bit sequence, possibly several times in sequence, until it no longer finds any code errors in the n-bit bit groups delivered by the serial-to-parallel converter, which means that these bit groups are actually the n-bit words The known arrangement thus synchronizes its serial-to-j ,, parallel converter by means of a control loop In a control of this type, subcircuits typically retroact on subcircuits connected in series with them This is particularly disadvantageous if the co-operating subcircuits are to be realized in different semiconductor technologies, depending upon . .
the speed of th- processing taking place in them In particular, it must be taken into consideration in this case that, in new oommunicatlon syste~s, the bit sequence frequencies of th- bit s-quences that are to be transmitted serially will be betwe-n 150 and 600 Mbit/s or even higher, and will thus require a relatively expensive T$L or ECL technology On the other hand, it is - 2~0~7 desirable, for cost reasons, to be able to use the CMOS
technology.
SUMMARY OF THE INVENTION
It is therefore the task of the invention to provide a circuit arrangement of the type mentioned above, which makes possible a realization of different subcircuits in different technologies to a greater extent than the known circuit arrangement.
The task is accomplished by a cirouit arrangement which converts a serial input bit sequence consisting of successive n-bit words to a parallel word format, a serial-to-parallel converter operates in an unsynchronized manner, i.e., with an arbitrary synchronization o~fset with respect to the word beginnings in the input bit sequence. A synchronizing circuit detects~the off et signal of the synchronization and provides an offset signal. There is connected in series with the converter a ~ -~
circuit whi¢h, in adcordande with the offset signal, rearranges bit groups~delivered by the serial-to-parallel converter in such `~
: ~ .
2 ~ 7 a way that complete words are delivered successively to n outputs of the circuit arrangement. Instead of a synchronizing circuit for the serial-to-parallel converter, a control circuit connected in series with the converter is used.
A circuit arrangement which converts a bit sequence, consisting of successive n-bit words, word by word from serial to parallel form, is characterized in that it contains a serial-to-parallel converter which converts the input bit sequence into n-bit bit groups with an arbitrary clock phase; a synchronizing -.,:
circuit which detects the word boundaries of the input bit sequence and, by comparing the word boundaries with the clock phase of the serial-to-parallel converter, produces a control signal indicating the synchronization offset of the serial-to-parallel converter; and a circuit which rearranges the n-bit bit groups from the serial-to-parallel converter word by word, and ~ `
delivers the n-bit words contained therein in parallel form under control of the control signal.
.`.
~ ~ ' ' ', : ~ ~ ', ' :
~ ~ ~4---`` 2~2~7 DESCRIPTION OF THE DRAWING
, ~. ..
The drawing shows a block diagram of the circuit arrangement according to the invention in the upper part and the bit groups appearing successively at different points of the circuit arrangement in the lower part.
. .
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
. ;~
At an input of the circuit arrangement shown in the drawing ~ -there is provided a bit sequence in serial form with a specific -~
bit clock rate, e.g., lS0 Mbit/s. This bit sequence contains succesoive words with n, for example, 8 bits each. The circuit arrangement has the task of converting this bit sequence from serial to parallel in a word-by-word manner, i.e., in such a way that, at n outputs, the bits of a first word, and then those of a second word, etc., will appear successively, in each case in parallel form. For the following example, we shall always start from the fact that n'i~ eq~ai to 8.
~ . . . .
~ ~5~
--.
.
2~2~07 `
The circuit arrangement contains a serial-to-parallel converter 1, into which the input bit sequence is inputted serially. A circuit for clock derivation (not shown) derives the bit clock from the input bit sequence and divides this by 8 with an arbitrary phase. The serial-to-parallel converter 1 is operated with this bit clock divided by 8 as the operating clock signal. The operating clock signal is designated as OC in the ~
drawing. The serial-to-parallel converter 1 thus converts its ~;
input bit sequence into 8-bit bit groups, which it delivers ~ i~
successively in parallel form at its eight outputs, at the clock rate of the operating clock.
Since the phase of the operating clock, OC, of the serial-to- ;
parallel converter 1 is fixed, but arbitrary, and is not synchronized with the phase of the word boundaries of the words -;
oontained in the input bit sequence, the serial-to-parallel converter 1 generally operates with a synchronization delay, so that the n-blt bit groups delivered by it at the output are not ld-ntical to the n-bit words contained successively in the input bit sequence but contain bi'ts of different words.
, -6- ~
:~
.- ~
~ 2~2~7 The drawing shows this in an example, in which several bit groups B1, B2, B3 delivered successively by the serial-to-parallel converter 1 are in each case shown as eight connected boxes representing eight bits and the bits belonging to a word are in each case symbolized by a specific pattern. In the example shown, a first bit group Bl contains two bits (empty boxes) which are received as the last bits of a word W1, and six bits (diagonally dashed boxes) of a successively received word W2. The remaining two bits of W2 are contained in a bit group ~;:
B2, which appears one operating clock period later at the outputs of the serial-to-parallel converter 1 and which contains the first six bits of a word W3 (checkered boxes) as additional bits. The two remaining bits of the word W3 are contained in a. . i bit group B3, which again appears an operating clock period later (checkered boxes), and which contains the first six bits (dark - ~ -boxes) of a next word W4 as additional bits. The points in time at which these bit groups appear at the outputs of the serial-to-parallel converter 1 are indicated by t1, t2 and t3. As already -~ ~
mentioned, they areiseparated by one clock-pulse period of the -;
; operating clock, OC, of the serial-to parallel converter 1. ::' ~
:
2~007 In this example, therefore, the synchronization delay has a value of 2 bit clock-pulse periods. (If the phase of the operating clock were two bit clock-pulse periods earlier, then the bit groups Bl through B3 would each contain a complete word.) According to the invention, the serial-to-parallel converter -~
is not synchronized with the word boundaries of the input bit sequence (in contrast to the known arrangement mentioned in the Description of the Prior Art), but retains its synchronization ;~
delay, which can amount to 1-7 bits, and in series with the converter there is connected a circuit which, under the control of synchronization delay, makes certain that the bits contained ; ~;
in the input bit sequence are delivered word-by-word in parallel form.
A synchronizing circuit 2 for detection of the synchronization delay is provided. This circuit receives the , ~ operating clock, OC, of the serial-to-parallel converter and the ~ , ..
input bit sequence. In a manner that is of no interest to the prèsent invention, the circuit detects the word boundaries of the successivè n-bit wdrds,in the input bit sequence, compares the phase of a clock derived from the word boundaries with the phase ~ i ' :~
2~2~7 of the operating clock, and determines the phase delay of the operating clock relative to the phase of the word boundaries as, for example, two-bit delay period shown in the drawing. The synchronizing circuit accordingly delivers an eight-bit control signal S at its output indicating the synchronization delay.
The circuit controlled by this control signal could be any -memory circuit, into which the n-bit bit groups, such as Bl -through B3, etc., delivered successively by the serial-to-parallel converter 1 are inputted for interim storage and, controlled in accordance with the synchronization delay, are - -~
delivered in such a way that eight bits of a single word appear in parallel form at the eight parallel outputs. ~ `t As an advantageous embodiment of the invention, instead of a ~ ~`
memory of this type, a simpler circuit is used, as shown in the drawi~ng. This circuit rearranges the 8-bit bit groups B1, B2, ~ ;
B3, etc., delivered successively by the serial-to-parallel conv-rter in such a way that complete words are delivered successively in parallel form. The circuit contains a delay circuit 3, which deliays each of the bit groups~Bi deliverèd ~ succ-ssively by the serial-to-parallel converter by one clock-:~ ;: _g_ ~ .
: ~ ,.
2~"~7 pulse period of the operating clock, OC. The delay circuit 3 has eight parallel outputs provided to lines 6. A bus 4 having eight parallel lines is connected to the output of the serial-to- - i parallel converter and makes available each bit group Bi delivered by the serial-to-parallel converter 1 without delay and in parallel form. A selection circuit 5 receives 16 bits from lines 6 and bus 4 and delivers a specific eight bits of each 16-bit group, as will be explained below.
The action of this circuit is illustrated in the drawing and is easily understandable. A portion of the circuit consisting of ~ ~.
the delay circuit 3, bus 4 and lines 6, form two bit groups delivered successively by the serial-to-parallel converter 1.
The circuit portion in each case forms a word with twice the bit count (i.e., 16 bits) by adding the bits of a second bit group in parallel to a first bit group.
For example, at a time t2 a 16-bit bit group BB2 i9 formed.
This contains, side by side, the bits of a bit group Bl, which -~
was delivered by the series-to-parallel converter 1 one clock-pulse period of the operating clock earlier, and the bits!of the bit group B2 delivered at the time t2. In the same manner, there : .
~ -10-~`~
-- 2 ~
was formed at a time t1 a bit group BBl, which is composed of the bits of a bit group Bo appearing one clock-pulse period earlier and the bits of the bit group B1 appearing at the time tl. The earlier formed bit groups appear above the dashed line as the output bits of the delay circuit 3, and the later bits appear below the dashed line as the output bits of the serial-to-parallel converter 1, which are delivered undelayed by the bus 4. Also, a bit group BB3, composed of the bit groups B2 and B3, appears at a later time t3.
A seen in the drawing, all of these 16-bit groups BBi have the property that they contain a complete word, whose bits are located side by side, and that this word is in the same bit positions in all bit groups, for example, in the positions 3 to ~ "~
10, counting from top to bottom.
;~ ~The subsequent selection circuit S must now only switch through~to its eight outputs those eight of its 16 input lines that~contain the bits of a complete word in parallel form. In the~example shown, these are lines 3-10, if all of the lines are numbered with the numbers i-16 from top to bottom. If thése ::
lines are switched through to the outputs, then the words Wl, W2, :: :
~ : -11-: ~ ::: :
2 ~ 2 ~
W3, which are contained in the above-mentioned bit positions in the bit groups BB1, BB2, BB3, appear successively at the times tl, t2, t3 etc~
The selection circuit 5 is a central gate matrix for ~;
switching through n of 2n input lines to n output lines. This is a 2n x n gate matrix with 2n signal inputs and n control inputs, -into whose control inputs a control word S is inputted into n ~ - , .
control inputs by means of a bus line n bits in width. In the example shown, this is a control word which, for example, has a 1 in the third bit position and a O in all other bit positions, and the gate matrix operates in such a way that, when this word is applied to its control inputs, it connects its input lines 3-10 with its eight output lines.
Aslde from slight gate delays, the gate matrix does not cause any delay of the words to be delivered, and, overall, the cirauit has the advantage that, immediately after the synchronizing circuit 2 has detected the synchronization offset, it delivers the successive words in the correct order. The delay byione period of the operating clock, OC, that a part of a word undergoes until the remaining part of the word is available, has ~-- 2 0 ~ 7 no harmful effect on the further processing of the parallellized words. The synchronizing circuit 2 uses a simple logic circuit for generation of the control signal S. In the example shown, for a synchronization offset of two bits, the circuit 2 delivers an 8-bit word which has a 1 in the third bit position and only 0- ~ ;~
bits otherwise.
The part of the synchronizing circuit that detects the word boundaries in the input bit sequence can be a Xnown circuit, such as is generally used for word synchronization, e.g., a circuit that detects a frame synchronous word in the input bit sequence, as a result of which the word boundaries of the words transmitted in the frame are fixed.
It is not an absolute requirement that the synchronizing clrcuit 2 receive the bit sequence in serial form as an input signal. A synchronizing circuit can be used that evaluates the sequence of n-bit bit groups delivered by the serial-to-parallel converter 1 and can find the word boundaries in a parallel format.
~ -13-
Claims (3)
1. A circuit arrangement which converts a bit sequence consisting of successive n-bit words, word by word from serial to parallel form, comprising:
a serial-to-parallel converter which converts the input bit sequence into n-bit bit groups with an arbitrary clock phase;
a synchronizing circuit which detects the word boundaries of the input bit sequence and, by comparing the word boundaries with the clock phase of the serial-to-parallel converter, produces a control signal indicating the synchronization offset of the serial-to-parallel converter; and a circuit which rearranges the n-bit bit groups from the serial-to-parallel converter, word by word, and delivers the n-bit words contained therein in parallel form under control of the control signal.
a serial-to-parallel converter which converts the input bit sequence into n-bit bit groups with an arbitrary clock phase;
a synchronizing circuit which detects the word boundaries of the input bit sequence and, by comparing the word boundaries with the clock phase of the serial-to-parallel converter, produces a control signal indicating the synchronization offset of the serial-to-parallel converter; and a circuit which rearranges the n-bit bit groups from the serial-to-parallel converter, word by word, and delivers the n-bit words contained therein in parallel form under control of the control signal.
2. A circuit arrangement as claimed in claim 1, wherein the circuit for rearranging the n-bit bit groups from the serial-to-parallel converter comprises:
a subcircuit which forms from every two successive n-bit bit groups delivered by the serial-to-parallel converter one 2n-bit bit group in which the bits of the second of two successive n-bit bit groups delivered by the serial-to-parallel converter are added in parallel to the bits of the first; and an n-out-of-2n selection circuit into which each 2n-bit bit group is transferred in parallel, and which switches a given part of n inputs lying side by side to its n outputs under control of the control signal.
a subcircuit which forms from every two successive n-bit bit groups delivered by the serial-to-parallel converter one 2n-bit bit group in which the bits of the second of two successive n-bit bit groups delivered by the serial-to-parallel converter are added in parallel to the bits of the first; and an n-out-of-2n selection circuit into which each 2n-bit bit group is transferred in parallel, and which switches a given part of n inputs lying side by side to its n outputs under control of the control signal.
3. A circuit arrangement as claimed in claim 2, wherein the subcircuit forming the 2n-bit bit groups comprises:
a delay circuit by which each n-bit bit group delivered by the serial-to-parallel converter in parallel form is delivered at n parallel outputs with a delay equal to one period of the clock signal of the serial-to-parallel converter; and a bus by which each n-bit bit group delivered by the serial-to-parallel converter in parallel form is delivered undelayed, so that a total of 2n outputs of the subcircuit provides a 2n-bit bit group in parallel form which contains, in a first part, a first of two successive n-bit bit groups delivered by the serial-to-parallel converter in parallel form and, in a second part, a second of said two successive n-bit bit groups.
a delay circuit by which each n-bit bit group delivered by the serial-to-parallel converter in parallel form is delivered at n parallel outputs with a delay equal to one period of the clock signal of the serial-to-parallel converter; and a bus by which each n-bit bit group delivered by the serial-to-parallel converter in parallel form is delivered undelayed, so that a total of 2n outputs of the subcircuit provides a 2n-bit bit group in parallel form which contains, in a first part, a first of two successive n-bit bit groups delivered by the serial-to-parallel converter in parallel form and, in a second part, a second of said two successive n-bit bit groups.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP3922482.1 | 1989-07-08 | ||
| DE19893922482 DE3922482A1 (en) | 1989-07-08 | 1989-07-08 | Series-parallel converter maintaining input word structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2020607A1 true CA2020607A1 (en) | 1991-01-09 |
Family
ID=6384553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2020607 Abandoned CA2020607A1 (en) | 1989-07-08 | 1990-07-06 | Circuit arrangement for word-by-word serial-to-parallel conversion |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH03139020A (en) |
| CA (1) | CA2020607A1 (en) |
| DE (1) | DE3922482A1 (en) |
| HU (1) | HUT57963A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE518865C2 (en) | 1998-12-22 | 2002-12-03 | Switchcore Ab | Converter for data in serial and parallel format, has twin port storage cells linked to data channels via database with buffer circuit |
-
1989
- 1989-07-08 DE DE19893922482 patent/DE3922482A1/en not_active Withdrawn
-
1990
- 1990-07-05 HU HU409690A patent/HUT57963A/en unknown
- 1990-07-06 JP JP17761990A patent/JPH03139020A/en active Pending
- 1990-07-06 CA CA 2020607 patent/CA2020607A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03139020A (en) | 1991-06-13 |
| DE3922482A1 (en) | 1991-01-17 |
| HU904096D0 (en) | 1990-12-28 |
| HUT57963A (en) | 1991-12-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Dead |