JPS624857B2 - - Google Patents

Info

Publication number
JPS624857B2
JPS624857B2 JP58090678A JP9067883A JPS624857B2 JP S624857 B2 JPS624857 B2 JP S624857B2 JP 58090678 A JP58090678 A JP 58090678A JP 9067883 A JP9067883 A JP 9067883A JP S624857 B2 JPS624857 B2 JP S624857B2
Authority
JP
Japan
Prior art keywords
lead
leads
glass
frame
tab
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58090678A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58212152A (ja
Inventor
Seishiro Oowaki
Michio Tanimoto
Motoharu Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58090678A priority Critical patent/JPS58212152A/ja
Publication of JPS58212152A publication Critical patent/JPS58212152A/ja
Publication of JPS624857B2 publication Critical patent/JPS624857B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/435—Shapes or dispositions of insulating layers on leadframes, e.g. bridging members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP58090678A 1983-05-25 1983-05-25 ガラス封止半導体装置の製造方法 Granted JPS58212152A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58090678A JPS58212152A (ja) 1983-05-25 1983-05-25 ガラス封止半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58090678A JPS58212152A (ja) 1983-05-25 1983-05-25 ガラス封止半導体装置の製造方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP50076565A Division JPS5841660B2 (ja) 1975-06-24 1975-06-24 ガラスフウシハンドウタイソウチノセイゾウホウホウオヨビ ソノホウホウニオイテモチイルリ−ドフレ−ム

Publications (2)

Publication Number Publication Date
JPS58212152A JPS58212152A (ja) 1983-12-09
JPS624857B2 true JPS624857B2 (enFirst) 1987-02-02

Family

ID=14005191

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58090678A Granted JPS58212152A (ja) 1983-05-25 1983-05-25 ガラス封止半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS58212152A (enFirst)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS613434A (ja) * 1984-06-15 1986-01-09 Ricoh Co Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
JPS58212152A (ja) 1983-12-09

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