JPS6227548B2 - - Google Patents

Info

Publication number
JPS6227548B2
JPS6227548B2 JP54070345A JP7034579A JPS6227548B2 JP S6227548 B2 JPS6227548 B2 JP S6227548B2 JP 54070345 A JP54070345 A JP 54070345A JP 7034579 A JP7034579 A JP 7034579A JP S6227548 B2 JPS6227548 B2 JP S6227548B2
Authority
JP
Japan
Prior art keywords
semiconductor element
element fixing
fixing plate
resin
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54070345A
Other languages
English (en)
Japanese (ja)
Other versions
JPS55162252A (en
Inventor
Koichi Hirata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP7034579A priority Critical patent/JPS55162252A/ja
Publication of JPS55162252A publication Critical patent/JPS55162252A/ja
Publication of JPS6227548B2 publication Critical patent/JPS6227548B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP7034579A 1979-06-05 1979-06-05 Semiconductor device Granted JPS55162252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7034579A JPS55162252A (en) 1979-06-05 1979-06-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7034579A JPS55162252A (en) 1979-06-05 1979-06-05 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS55162252A JPS55162252A (en) 1980-12-17
JPS6227548B2 true JPS6227548B2 (enFirst) 1987-06-15

Family

ID=13428731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7034579A Granted JPS55162252A (en) 1979-06-05 1979-06-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS55162252A (enFirst)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5861654A (ja) * 1981-10-09 1983-04-12 Toshiba Corp 半導体装置
JPS58111966U (ja) * 1982-01-25 1983-07-30 松下電器産業株式会社 集積回路部品
US7989933B1 (en) * 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS523217Y2 (enFirst) * 1973-05-16 1977-01-24
JPS5116698U (enFirst) * 1974-07-24 1976-02-06
JPS5845821B2 (ja) * 1976-03-05 1983-10-12 株式会社日立製作所 半導体装置
JPS54180668U (enFirst) * 1978-06-09 1979-12-20

Also Published As

Publication number Publication date
JPS55162252A (en) 1980-12-17

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