JPS6245708B2 - - Google Patents

Info

Publication number
JPS6245708B2
JPS6245708B2 JP58000840A JP84083A JPS6245708B2 JP S6245708 B2 JPS6245708 B2 JP S6245708B2 JP 58000840 A JP58000840 A JP 58000840A JP 84083 A JP84083 A JP 84083A JP S6245708 B2 JPS6245708 B2 JP S6245708B2
Authority
JP
Japan
Prior art keywords
gate electrode
polycrystalline silicon
element region
electrode material
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58000840A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59125650A (ja
Inventor
Hiroshi Kobayashi
Yoshihisa Mizutani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP58000840A priority Critical patent/JPS59125650A/ja
Publication of JPS59125650A publication Critical patent/JPS59125650A/ja
Publication of JPS6245708B2 publication Critical patent/JPS6245708B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D64/0131—
    • H10D64/0132—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP58000840A 1983-01-07 1983-01-07 半導体装置の製造方法 Granted JPS59125650A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58000840A JPS59125650A (ja) 1983-01-07 1983-01-07 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58000840A JPS59125650A (ja) 1983-01-07 1983-01-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS59125650A JPS59125650A (ja) 1984-07-20
JPS6245708B2 true JPS6245708B2 (member.php) 1987-09-28

Family

ID=11484810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58000840A Granted JPS59125650A (ja) 1983-01-07 1983-01-07 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS59125650A (member.php)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045053A (ja) * 1983-08-22 1985-03-11 Mitsubishi Electric Corp 半導体装置
JP2829614B2 (ja) * 1988-08-26 1998-11-25 株式会社日立製作所 相補型ｍｏｓ集積回路の製造方法
JP2667282B2 (ja) * 1990-05-29 1997-10-27 沖電気工業株式会社 半導体装置及びその配線形成方法
US6130123A (en) * 1998-06-30 2000-10-10 Intel Corporation Method for making a complementary metal gate electrode technology
US6599831B1 (en) * 2002-04-30 2003-07-29 Advanced Micro Devices, Inc. Metal gate electrode using silicidation and method of formation thereof
JP2005228761A (ja) * 2004-02-10 2005-08-25 Rohm Co Ltd 半導体装置及びその製造方法
TWI252539B (en) 2004-03-12 2006-04-01 Toshiba Corp Semiconductor device and manufacturing method therefor
EP1782466A2 (en) * 2004-08-13 2007-05-09 Koninklijke Philips Electronics N.V. Dual gate cmos fabrication
JP4938262B2 (ja) * 2004-08-25 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2006245167A (ja) * 2005-03-02 2006-09-14 Toshiba Corp 半導体装置及びその製造方法
US7151023B1 (en) * 2005-08-01 2006-12-19 International Business Machines Corporation Metal gate MOSFET by full semiconductor metal alloy conversion
US7183613B1 (en) * 2005-11-15 2007-02-27 International Business Machines Corporation Method and structure for enhancing both NMOSFET and PMOSFET performance with a stressed film
JP2010161400A (ja) * 2010-03-11 2010-07-22 Rohm Co Ltd 半導体装置とその製造方法

Also Published As

Publication number Publication date
JPS59125650A (ja) 1984-07-20

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