JPS6244429B2 - - Google Patents

Info

Publication number
JPS6244429B2
JPS6244429B2 JP54134316A JP13431679A JPS6244429B2 JP S6244429 B2 JPS6244429 B2 JP S6244429B2 JP 54134316 A JP54134316 A JP 54134316A JP 13431679 A JP13431679 A JP 13431679A JP S6244429 B2 JPS6244429 B2 JP S6244429B2
Authority
JP
Japan
Prior art keywords
layer
substrate
conductor layer
bit
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54134316A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5591158A (en
Inventor
Fuiritsupu Nooburu Junia Uenderu
Aran Yunisu Richaado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5591158A publication Critical patent/JPS5591158A/ja
Publication of JPS6244429B2 publication Critical patent/JPS6244429B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P95/064—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10P50/667—
    • H10W20/075—
    • H10W20/495—
    • H10W72/00—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/901—Capacitive junction

Landscapes

  • Semiconductor Memories (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Static Random-Access Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP13431679A 1978-12-26 1979-10-19 Method of fabricating semiconductor device Granted JPS5591158A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/973,219 US4222816A (en) 1978-12-26 1978-12-26 Method for reducing parasitic capacitance in integrated circuit structures

Publications (2)

Publication Number Publication Date
JPS5591158A JPS5591158A (en) 1980-07-10
JPS6244429B2 true JPS6244429B2 (cg-RX-API-DMAC10.html) 1987-09-21

Family

ID=25520641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13431679A Granted JPS5591158A (en) 1978-12-26 1979-10-19 Method of fabricating semiconductor device

Country Status (4)

Country Link
US (1) US4222816A (cg-RX-API-DMAC10.html)
EP (1) EP0012863B1 (cg-RX-API-DMAC10.html)
JP (1) JPS5591158A (cg-RX-API-DMAC10.html)
DE (1) DE2963453D1 (cg-RX-API-DMAC10.html)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295924A (en) * 1979-12-17 1981-10-20 International Business Machines Corporation Method for providing self-aligned conductor in a V-groove device
JPS5793572A (en) * 1980-12-03 1982-06-10 Nec Corp Manufacture of semiconductor device
JPS59161069A (ja) * 1983-03-04 1984-09-11 Oki Electric Ind Co Ltd Ｍｏｓ型半導体装置の製造方法
JPS6045057A (ja) * 1983-08-23 1985-03-11 Toshiba Corp 固体撮像装置の製造方法
US4478679A (en) * 1983-11-30 1984-10-23 Storage Technology Partners Self-aligning process for placing a barrier metal over the source and drain regions of MOS semiconductors
US4594769A (en) * 1984-06-15 1986-06-17 Signetics Corporation Method of forming insulator of selectively varying thickness on patterned conductive layer
US5734188A (en) * 1987-09-19 1998-03-31 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
EP0329569B1 (en) * 1988-02-17 1995-07-05 Fujitsu Limited Semiconductor device with a thin insulating film
US5214304A (en) * 1988-02-17 1993-05-25 Fujitsu Limited Semiconductor device
US5917211A (en) * 1988-09-19 1999-06-29 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
US5589423A (en) * 1994-10-03 1996-12-31 Motorola Inc. Process for fabricating a non-silicided region in an integrated circuit
US6342681B1 (en) * 1997-10-15 2002-01-29 Avx Corporation Surface mount coupler device
DE19753782A1 (de) * 1997-12-04 1999-06-10 Inst Halbleiterphysik Gmbh Verfahren zur Planarisierung von Silizium-Wafern

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH573661A5 (cg-RX-API-DMAC10.html) * 1973-01-02 1976-03-15 Ibm
US3841926A (en) * 1973-01-02 1974-10-15 Ibm Integrated circuit fabrication process
US3976524A (en) * 1974-06-17 1976-08-24 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
DE2547792C3 (de) * 1974-10-25 1978-08-31 Hitachi, Ltd., Tokio Verfahren zur Herstellung eines Halbleiterbauelementes
US3975220A (en) * 1975-09-05 1976-08-17 International Business Machines Corporation Diffusion control for controlling parasitic capacitor effects in single FET structure arrays
US4045594A (en) * 1975-12-31 1977-08-30 Ibm Corporation Planar insulation of conductive patterns by chemical vapor deposition and sputtering
DE2629996A1 (de) * 1976-07-03 1978-01-05 Ibm Deutschland Verfahren zur passivierung und planarisierung eines metallisierungsmusters
US4095251A (en) * 1976-08-19 1978-06-13 International Business Machines Corporation Field effect transistors and fabrication of integrated circuits containing the transistors
US4070501A (en) * 1976-10-28 1978-01-24 Ibm Corporation Forming self-aligned via holes in thin film interconnection systems

Also Published As

Publication number Publication date
EP0012863A2 (de) 1980-07-09
EP0012863B1 (de) 1982-07-28
US4222816A (en) 1980-09-16
DE2963453D1 (en) 1982-09-16
JPS5591158A (en) 1980-07-10
EP0012863A3 (en) 1980-10-15

Similar Documents

Publication Publication Date Title
US3699646A (en) Integrated circuit structure and method for making integrated circuit structure
US3841926A (en) Integrated circuit fabrication process
US4295924A (en) Method for providing self-aligned conductor in a V-groove device
JPH0580142B2 (cg-RX-API-DMAC10.html)
JPH0685086A (ja) 高集積素子用微細コンタクト形成方法
GB1589288A (en) Field effect transistors
JPS6244429B2 (cg-RX-API-DMAC10.html)
JPH06177345A (ja) 半導体メモリおよびその製造方法
JPS6249750B2 (cg-RX-API-DMAC10.html)
US5259924A (en) Integrated circuit fabrication process to reduce critical dimension loss during etching
JPS60124967A (ja) 集積回路構造体
JPS5944789B2 (ja) 自己整合型横方向バイポ−ラトランジスタの製造方法
JPH0712058B2 (ja) 半導体装置およびその製造方法
KR100261210B1 (ko) 디커플링 커패시터의 형성방법
KR0183899B1 (ko) 자기 정렬 콘택 홀 형성 방법
JPH0736423B2 (ja) 半導体装置の製造方法
KR100304946B1 (ko) 반도체장치의제조방법
JPS61129872A (ja) 半導体装置の製造方法
KR970005031A (ko) 저저항 배선구조를 갖는 반도체장치 및 그 제조방법
KR0166203B1 (ko) 반도체장치의 콘택 형성방법
KR940001258B1 (ko) BiCMOS소자의 제조방법
JP3463456B2 (ja) プロセス評価素子
KR0141949B1 (ko) 반도체소자의 제조방법
JP3532352B2 (ja) 半導体装置の製造方法
KR100218727B1 (ko) 반도체 소자의 콘택홀 형성방법