JPS6228578B2 - - Google Patents

Info

Publication number
JPS6228578B2
JPS6228578B2 JP53023086A JP2308678A JPS6228578B2 JP S6228578 B2 JPS6228578 B2 JP S6228578B2 JP 53023086 A JP53023086 A JP 53023086A JP 2308678 A JP2308678 A JP 2308678A JP S6228578 B2 JPS6228578 B2 JP S6228578B2
Authority
JP
Japan
Prior art keywords
silicon dioxide
film
dioxide film
semiconductor substrate
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53023086A
Other languages
English (en)
Japanese (ja)
Other versions
JPS54115085A (en
Inventor
Takashi Matsumoto
Takaharu Nawata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Original Assignee
CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHO ERU ESU AI GIJUTSU KENKYU KUMIAI filed Critical CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Priority to JP2308678A priority Critical patent/JPS54115085A/ja
Priority to US06/015,897 priority patent/US4292156A/en
Publication of JPS54115085A publication Critical patent/JPS54115085A/ja
Publication of JPS6228578B2 publication Critical patent/JPS6228578B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P30/40—
    • H10P14/61—
    • H10P50/283—
    • H10P50/692—
    • H10P50/695—
    • H10W10/0121—
    • H10W10/13—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/143—Shadow masking

Landscapes

  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
JP2308678A 1978-02-28 1978-02-28 Method of fabricating semiconductor Granted JPS54115085A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2308678A JPS54115085A (en) 1978-02-28 1978-02-28 Method of fabricating semiconductor
US06/015,897 US4292156A (en) 1978-02-28 1979-02-28 Method of manufacturing semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2308678A JPS54115085A (en) 1978-02-28 1978-02-28 Method of fabricating semiconductor

Publications (2)

Publication Number Publication Date
JPS54115085A JPS54115085A (en) 1979-09-07
JPS6228578B2 true JPS6228578B2 (enExample) 1987-06-22

Family

ID=12100606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2308678A Granted JPS54115085A (en) 1978-02-28 1978-02-28 Method of fabricating semiconductor

Country Status (2)

Country Link
US (1) US4292156A (enExample)
JP (1) JPS54115085A (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4465705A (en) * 1980-05-19 1984-08-14 Matsushita Electric Industrial Co., Ltd. Method of making semiconductor devices
US4361600A (en) * 1981-11-12 1982-11-30 General Electric Company Method of making integrated circuits
US4460434A (en) * 1982-04-15 1984-07-17 At&T Bell Laboratories Method for planarizing patterned surfaces
JPS5952847A (ja) * 1982-09-20 1984-03-27 Mitsubishi Electric Corp 半導体装置の製造方法
US4435446A (en) 1982-11-15 1984-03-06 Hewlett-Packard Company Edge seal with polysilicon in LOCOS process
JPS59138379A (ja) * 1983-01-27 1984-08-08 Toshiba Corp 半導体装置の製造方法
US4486266A (en) * 1983-08-12 1984-12-04 Tektronix, Inc. Integrated circuit method
US4477310A (en) * 1983-08-12 1984-10-16 Tektronix, Inc. Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas
DE3405162A1 (de) * 1984-02-14 1985-08-22 Bosch Gmbh Robert Polarographischer sauerstoffmessfuehler
US4561172A (en) * 1984-06-15 1985-12-31 Texas Instruments Incorporated Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions
US4538343A (en) * 1984-06-15 1985-09-03 Texas Instruments Incorporated Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking
JPS6281727A (ja) * 1985-10-05 1987-04-15 Fujitsu Ltd 埋込型素子分離溝の形成方法
US4824795A (en) * 1985-12-19 1989-04-25 Siliconix Incorporated Method for obtaining regions of dielectrically isolated single crystal silicon
GB8607822D0 (en) * 1986-03-27 1986-04-30 Plessey Co Plc Iii-v semiconductor devices
US4758530A (en) * 1986-12-08 1988-07-19 Delco Electronics Corporation Doubly-self-aligned hole-within-a-hole structure in semiconductor fabrication involving a double LOCOS process aligned with sidewall spacers
US4968640A (en) * 1987-02-10 1990-11-06 Industrial Technology Research Institute Isolation structures for integrated circuits
US5149669A (en) * 1987-03-06 1992-09-22 Seiko Instruments Inc. Method of forming an isolation region in a semiconductor device
US4775644A (en) * 1987-06-03 1988-10-04 Lsi Logic Corporation Zero bird-beak oxide isolation scheme for integrated circuits
US4863562A (en) * 1988-02-11 1989-09-05 Sgs-Thomson Microelectronics, Inc. Method for forming a non-planar structure on the surface of a semiconductor substrate
KR100189733B1 (ko) * 1996-07-22 1999-06-01 구본준 반도체장치의 소자분리막 형성방법
KR100668509B1 (ko) * 2005-06-10 2007-01-12 주식회사 하이닉스반도체 비대칭 스텝구조의 게이트를 갖는 반도체소자의 제조 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL157662B (nl) * 1969-05-22 1978-08-15 Philips Nv Werkwijze voor het etsen van een oppervlak onder toepassing van een etsmasker, alsmede voorwerpen, verkregen door toepassing van deze werkwijze.
US3675314A (en) * 1970-03-12 1972-07-11 Alpha Ind Inc Method of producing semiconductor devices
GB1437112A (en) * 1973-09-07 1976-05-26 Mullard Ltd Semiconductor device manufacture
US3966514A (en) * 1975-06-30 1976-06-29 Ibm Corporation Method for forming dielectric isolation combining dielectric deposition and thermal oxidation
US3961999A (en) * 1975-06-30 1976-06-08 Ibm Corporation Method for forming recessed dielectric isolation with a minimized "bird's beak" problem

Also Published As

Publication number Publication date
JPS54115085A (en) 1979-09-07
US4292156A (en) 1981-09-29

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