JPS6222270B2 - - Google Patents

Info

Publication number
JPS6222270B2
JPS6222270B2 JP53131658A JP13165878A JPS6222270B2 JP S6222270 B2 JPS6222270 B2 JP S6222270B2 JP 53131658 A JP53131658 A JP 53131658A JP 13165878 A JP13165878 A JP 13165878A JP S6222270 B2 JPS6222270 B2 JP S6222270B2
Authority
JP
Japan
Prior art keywords
gate electrode
electrode layer
semiconductor substrate
layer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53131658A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5559759A (en
Inventor
Yoshiaki Oonishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13165878A priority Critical patent/JPS5559759A/ja
Priority to US06/083,660 priority patent/US4264965A/en
Priority to DE19792943381 priority patent/DE2943381A1/de
Publication of JPS5559759A publication Critical patent/JPS5559759A/ja
Publication of JPS6222270B2 publication Critical patent/JPS6222270B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP13165878A 1978-10-27 1978-10-27 Semiconductor device Granted JPS5559759A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP13165878A JPS5559759A (en) 1978-10-27 1978-10-27 Semiconductor device
US06/083,660 US4264965A (en) 1978-10-27 1979-10-11 Dummy cell structure for MIS dynamic memories
DE19792943381 DE2943381A1 (de) 1978-10-27 1979-10-26 Blindzelle fuer dynamische speicher mit direktem zugriff

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13165878A JPS5559759A (en) 1978-10-27 1978-10-27 Semiconductor device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP58209048A Division JPS59107564A (ja) 1983-11-09 1983-11-09 半導体装置
JP58209049A Division JPS59107565A (ja) 1983-11-09 1983-11-09 半導体装置

Publications (2)

Publication Number Publication Date
JPS5559759A JPS5559759A (en) 1980-05-06
JPS6222270B2 true JPS6222270B2 (enExample) 1987-05-16

Family

ID=15063191

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13165878A Granted JPS5559759A (en) 1978-10-27 1978-10-27 Semiconductor device

Country Status (3)

Country Link
US (1) US4264965A (enExample)
JP (1) JPS5559759A (enExample)
DE (1) DE2943381A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57186354A (en) * 1981-05-13 1982-11-16 Hitachi Ltd Semiconductor memory storage and manufacture thereof
DE3138947A1 (de) * 1981-09-30 1983-04-21 Siemens AG, 1000 Berlin und 8000 München Speicherzelle mit einem doppel-gate feldeffekttransistor und verfahren zu ihrem betrieb
JPS59172761A (ja) * 1983-03-23 1984-09-29 Hitachi Ltd 半導体装置
JP2509706B2 (ja) * 1989-08-18 1996-06-26 株式会社東芝 マスクｒｏｍの製造方法
KR0121992B1 (ko) * 1993-03-03 1997-11-12 모리시다 요이치 반도체장치 및 그 제조방법
JP3962638B2 (ja) * 2002-06-18 2007-08-22 株式会社東芝 半導体記憶装置、及び、半導体装置
JP2011071173A (ja) * 2009-09-24 2011-04-07 Elpida Memory Inc 半導体装置、半導体装置の製造方法および半導体装置の制御方法
KR20140010815A (ko) * 2012-07-17 2014-01-27 에스케이하이닉스 주식회사 Ｍｏｓ 커패시터, 그 형성 방법 및 그를 이용한 반도체 장치

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4195357A (en) * 1978-06-15 1980-03-25 Texas Instruments Incorporated Median spaced dummy cell layout for MOS random access memory

Also Published As

Publication number Publication date
DE2943381A1 (de) 1980-05-22
JPS5559759A (en) 1980-05-06
US4264965A (en) 1981-04-28

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