JPS62108577A - 混成集積回路 - Google Patents

混成集積回路

Info

Publication number
JPS62108577A
JPS62108577A JP60249456A JP24945685A JPS62108577A JP S62108577 A JPS62108577 A JP S62108577A JP 60249456 A JP60249456 A JP 60249456A JP 24945685 A JP24945685 A JP 24945685A JP S62108577 A JPS62108577 A JP S62108577A
Authority
JP
Japan
Prior art keywords
high frequency
fet
frequency
grounding
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60249456A
Other languages
English (en)
Other versions
JPH0799753B2 (ja
Inventor
Kenji Watanabe
謙二 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60249456A priority Critical patent/JPH0799753B2/ja
Publication of JPS62108577A publication Critical patent/JPS62108577A/ja
Publication of JPH0799753B2 publication Critical patent/JPH0799753B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、高周波用ＦＥＴの高周波接地および自己バイ
アス方法に関し、特に混成集積回路基板上での接地方法
に関し、更に詳しくは、回路基板にあけられたスルーホ
ール上に固着されたコンデンサと、高周波用ＦＥＴの接
地電極を接続することにより高周波用ＦＥＴを高周波接
地し、更に、自己バイアスする方法に関する。
〔従来の技術〕
従来、高周波用ＦＥＴ　（例えばＧａＡｓＦＥＴなど）
を含む混成集積回路において、高周波用ＦＥＴを接地す
る場合は、第２図（ａ）の平面図、および第２図（ｂ）
の断面図に示すように接地導体１上に分割され固着され
た導体膜回路２を有する絶縁基板３の間に高周波用ＦＥ
Ｔ４と両側にコンデンサ５が接地導体１に固着されてお
り、このコンデンサ５の上面電極６と高周波用ＦＥＴ４
の接地電極７をワイヤー（金、アルミニウム線など）８
で接続することにより高周波接地を行い、更に分割され
た絶縁基板３上の導体膜回路２とコンデンサ６を使用し
て自己バイアス回路を形成し、高周波用ＦＥＴにバイア
スを印加していた。
〔発明が解決しようとする問題点〕
上述した従来の接地方法では、高周波用ＦＥＴを自己バ
イアスで使用する場合基板を分割して使用しているため
、部品点数が増加し、組立歩留の低下及び、高価格とな
る欠点がある。
本発明の目的は、絶縁基板を分割することなく高周波用
ＦＥＴの高周波接地および自己バイアスが可能となり、
その結果部品材料の低減、組立歩留りの向上、および低
廉化の達成できる混成集積回路、特に高周波用ＦＥＴの
高周波接地および自己バイアス方法を提供することにあ
る。
〔問題点を解決するための手段〕
本発明の高周波用ＦＥＴの高周波接地および自己バイア
ス方法は、表面に導体膜回路が形成され、かつスルーホ
ールのあけられた回路基板を接地導体上に固着し、前記
回路基板上に接地電極を有する高周波用ＦＥＴを固着す
ると共に前記回路基板にあけられたスルーホール上にコ
ンデンサを固着し、該コンデンサの上部電極と前記高周
波用ＦＥＴの接地電極とを接続することにより高周波接
地を行い、更に自己バイアスできるように構成されてい
る。
〔実施例〕
次に、本発明の実施例について図面を参照して説明する
。
第１図（ａ＞、（ｂ）は、本発明の一実施例を説明する
ための平面図およびｘ−ｘ’線の断面図である。第１図
（ａ＞、（ｂ＞において接地導体１の上に導体膜回路２
を有する絶縁基板３が固着されており同基板内にあけら
れたスルーホール９の内面には、導体膜１０が形成され
ており、接地導体１と、回路基板の上面とを接続してい
る。更に、このスルーホール９上にコンデンサ５が固着
されており、このコンデンサ５の上面電極６と同一絶縁
基板３上に固着された高周波用ＦＥＴ４の接地電極７を
ワイヤー８で接続することにより、接地導体１との間で
高周波接地をとり、更に、このコンデンサ５を通して自
己バイアス回路を形成し高周波用ＦＥＴ４にバイアスを
行っている。
〔発明の効果〕
以上説明したように、本発明は、スルーホール上にコン
デンサを固着して使用することにより、絶縁基板を分割
して使用する必要がなく、高周波用ＦＥＴの高周波接地
および自己バイアスが可能となり、その結果部品材料の
低減、組立歩留の向上、および低廉化を達成することが
できる。
【図面の簡単な説明】
第１図（ａ）、（ｂ）は、本発明の一実施例を説明する
ための平面図およびｘ−ｘ’線断面図、第２図（ａ）、
（ｂ）は従来の混成集積回路の一例の場合を説明するた
めの平面図およびＹ−Ｙ”線断面図である。 １・・・接地導体、２・・・導体膜回路、３・・・絶縁
基板、４・・・高周波用ＦＥＴ、５・・・コンデンサ、
６・・・コンデンサ上面電極、７・・・接地電極、８・
・・ワイヤ、９・・・スルーホール、１０・・・導体膜
。 第１　図 （（２）　　　　　　　　　　　　　　　　　　　　　
　（ｂ）第　２　圀

Claims (1)

    【特許請求の範囲】
  1. 表面に導体膜回路が形成され、かつスルーホールのあけ
    られた回路基板を接地導体上に固着し、前記回路基板上
    に接地電極を有する高周波用ＦＥＴを固着すると共に前
    記回路基板にあけられたスルーホール上にコンデンサを
    固着し、該コンデンサの上部電極と前記高周波用ＦＥＴ
    の接地電極とを接続することを特徴とする高周波用ＦＥ
    Ｔの高周波接地および自己バイアス方法。
JP60249456A 1985-11-06 1985-11-06 混成集積回路 Expired - Lifetime JPH0799753B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60249456A JPH0799753B2 (ja) 1985-11-06 1985-11-06 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60249456A JPH0799753B2 (ja) 1985-11-06 1985-11-06 混成集積回路

Publications (2)

Publication Number Publication Date
JPS62108577A true JPS62108577A (ja) 1987-05-19
JPH0799753B2 JPH0799753B2 (ja) 1995-10-25

Family

ID=17193228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60249456A Expired - Lifetime JPH0799753B2 (ja) 1985-11-06 1985-11-06 混成集積回路

Country Status (1)

Country Link
JP (1) JPH0799753B2 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0327599A (ja) * 1988-11-02 1991-02-05 Robert Bosch Gmbh 電子制御装置
WO2002023620A3 (en) * 2000-09-15 2003-03-27 Hei Inc Connection for conducting high frequency signal between a circuit and a discrete electrical component
WO2008041682A1 (fr) * 2006-10-02 2008-04-10 Kabushiki Kaisha Toshiba Dispositif à semi-conducteur

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5756953A (en) * 1981-08-10 1982-04-05 Nec Corp Transistor
JPS59123270A (ja) * 1982-12-28 1984-07-17 Nec Corp モノリシツク回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5756953A (en) * 1981-08-10 1982-04-05 Nec Corp Transistor
JPS59123270A (ja) * 1982-12-28 1984-07-17 Nec Corp モノリシツク回路

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0327599A (ja) * 1988-11-02 1991-02-05 Robert Bosch Gmbh 電子制御装置
WO2002023620A3 (en) * 2000-09-15 2003-03-27 Hei Inc Connection for conducting high frequency signal between a circuit and a discrete electrical component
US6646521B1 (en) 2000-09-15 2003-11-11 Hei, Inc. Connection for conducting high frequency signal between a circuit and a discrete electric component
WO2008041682A1 (fr) * 2006-10-02 2008-04-10 Kabushiki Kaisha Toshiba Dispositif à semi-conducteur
JPWO2008041682A1 (ja) * 2006-10-02 2010-02-04 株式会社東芝 半導体装置
JP5085552B2 (ja) * 2006-10-02 2012-11-28 株式会社東芝 半導体装置
US8357942B2 (en) 2006-10-02 2013-01-22 Kabushiki Kaisha Toshiba Semiconductor device with a peripheral circuit formed therein

Also Published As

Publication number Publication date
JPH0799753B2 (ja) 1995-10-25

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