JPH0799753B2 - 混成集積回路 - Google Patents

混成集積回路

Info

Publication number
JPH0799753B2
JPH0799753B2 JP60249456A JP24945685A JPH0799753B2 JP H0799753 B2 JPH0799753 B2 JP H0799753B2 JP 60249456 A JP60249456 A JP 60249456A JP 24945685 A JP24945685 A JP 24945685A JP H0799753 B2 JPH0799753 B2 JP H0799753B2
Authority
JP
Japan
Prior art keywords
capacitor
insulating substrate
high frequency
fet
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60249456A
Other languages
English (en)
Other versions
JPS62108577A (ja
Inventor
謙二 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60249456A priority Critical patent/JPH0799753B2/ja
Publication of JPS62108577A publication Critical patent/JPS62108577A/ja
Publication of JPH0799753B2 publication Critical patent/JPH0799753B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高周波用FETの高周波接地および自己バイアス
方法に適した混成集積回路に係わり、特に混成集積回路
基板上での接地方法に関し、更に詳しくは、回路基板に
あけられたスルーホール上に固着されたコンデンサと、
高周波用FETの接地電極を接続することにより高周波用F
ETを高周波接地し、更に、自己バイアスする方法に関す
る。
〔従来の技術〕
従来、高周波用FET（例えばGaAsFETなど）を含む混成集
積回路において、高周波用FETを接地する場合は、第２
図（ａ）の平面図、および第２図（ｂ）の断面図に示す
ように接地導体１上に分割され固着された導体膜回路２
を有する絶縁基板３の間に高周波用FET4と両側にコンデ
ンサ５が接地導体１に固着されており、このコンデンサ
５の上面電極６と高周波用FET4の接地電極７をワイヤー
（金、アルミニウム線など）８で接続することにより高
周波接地を行い、更に分割された絶縁基板３上の導体膜
回路２とコンデンサ６を使用して自己バイアス回路を形
成し、高周波用FETにバイアスを印加していた。
〔発明が解決しようとする問題点〕
上述した従来の接地方法では、高周波用FETを自己バイ
アスで使用する場合基板を分割して使用しているため、
部品点数が増加し、組立歩留の低下及び、高価格となる
欠点がある。
本発明の目的は、絶縁基板を分割することなく高周波用
FETの高周波接地および自己バイアスが可能となり、そ
の結果部品材料の低減、組立歩留りの向上、および低廉
化の達成できる混成集積回路を提供することにある。
〔問題点を解決するための手段〕
本発明の特徴は、表面に導体膜回路が形成され、接地導
体上に固着された絶縁基板と、接地電極を有する高周波
用FETと、上面に電極を有するコンデンサと、前記高周
波FETの接地電極と前記コンデンサの上面の電極とを接
続する手段とを有し、前記高周波FETと前記コンデンサ
とが一方向に配列され、該配列の両側に前記導体膜回路
がそれぞれ位置している混成集積回路において、前記高
周波FETとコンデンサとの配列下から前記両側の導体膜
回路下まで前記絶縁基板が一体的に形成され、前記高周
波FETの下面が前記絶縁基板の表面に固着され、前記コ
ンデンサの下面が前記絶縁基板の表面に固着され、かつ
前記コンデンサ直下の前記絶縁基板の箇所にスルーホー
ルが形成され、前記スルーホールの内面に形成された導
電膜を通して前記コンデンサの下面が前記接地導体に接
続されている混成集積回路にある。
〔実施例〕
次に、本発明の実施例について図面を参照して説明す
る。
第１図（ａ），（ｂ）は、本発明の一実施例を説明する
ための平面図およびＸ−Ｘ′線の断面図である。第１図
（ａ），（ｂ）において接地導体１の上に導体膜回路２
を有する絶縁基板３が固着されており同基板内にあけら
れたスルーホール９の内面には、導体膜10が形成されて
おり、接地導体１と、回路基板の上面とを接続してい
る。更に、このスルーホール９上にコンデンサ５が固着
されており、このコンデンサ５の上面電極６と同一絶縁
基板３上に固着された高周波用FET4の接地電極７をワイ
ヤー８で接続することにより、接地導体１との間で高周
波接地をとり、更に、このコンデンサ５を通して自己バ
イアス回路を形成し高周波用FET4にバイアスを行ってい
る。
〔発明の効果〕
以上説明したように、本発明は、スルーホール上にコン
デンサを固着して使用することにより、絶縁基板を分割
して使用する必要がなく、高周波用FETの高周波接地お
よび自己バイアスが可能となり、その結果部品材料の低
減、組立歩留の向上、および低廉化を達成することがで
きる。
【図面の簡単な説明】
第１図（ａ），（ｂ）は、本発明の一実施例を説明する
ための平面図およびＸ−Ｘ′線断面図、第２図（ａ），
（ｂ）は従来の混成集積回路の一例の場合を説明するた
めの平面図およびＹ−Ｙ′線断面図である。 １……接地導体、２……導体膜回路、３……絶縁基板、
４……高周波用FET、５……コンデンサ、６……コンデ
ンサ上面電極、７……接地電極、８……ワイヤ、９……
スルーホール、10……導体膜。

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】表面に導体膜回路が形成され、接地導体上
    に固着された絶縁基板と、接地電極を有する高周波用FE
    Tと、上面に電極を有するコンデンサと、前記高周波FET
    の接地電極と前記コンデンサの上面の電極とを接続する
    手段とを有し、前記高周波FETと前記コンテンサとが一
    方向に配列され、該配列の両側に前記導体膜回路がそれ
    ぞれ位置している混成集積回路において、 前記高周波FETとコンデンサとの配列下から前記両側の
    導体膜回路下まで前記絶縁基板が一体的に形成され、前
    記高周波FETの下面が前記絶縁基板の表面に固着され、
    前記コンデンサの下面が前記絶縁基板の表面に固着さ
    れ、前記コンデンサ直下の前記絶縁基板の箇所にスルー
    ホールが形成され、前記スルーホールの内面に形成され
    た導電膜を通して前記コンデンサの下面が前記接地導体
    に接続されていることを特徴とする混成集積回路。
JP60249456A 1985-11-06 1985-11-06 混成集積回路 Expired - Lifetime JPH0799753B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60249456A JPH0799753B2 (ja) 1985-11-06 1985-11-06 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60249456A JPH0799753B2 (ja) 1985-11-06 1985-11-06 混成集積回路

Publications (2)

Publication Number Publication Date
JPS62108577A JPS62108577A (ja) 1987-05-19
JPH0799753B2 true JPH0799753B2 (ja) 1995-10-25

Family

ID=17193228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60249456A Expired - Lifetime JPH0799753B2 (ja) 1985-11-06 1985-11-06 混成集積回路

Country Status (1)

Country Link
JP (1) JPH0799753B2 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3837206C2 (de) * 1988-11-02 1998-07-23 Bosch Gmbh Robert Elektrisches Schaltgerät
US6646521B1 (en) * 2000-09-15 2003-11-11 Hei, Inc. Connection for conducting high frequency signal between a circuit and a discrete electric component
KR101058991B1 (ko) * 2006-10-02 2011-08-23 가부시끼가이샤 도시바 반도체 장치

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5756953A (en) * 1981-08-10 1982-04-05 Nec Corp Transistor
JPS59123270A (ja) * 1982-12-28 1984-07-17 Nec Corp モノリシツク回路

Also Published As

Publication number Publication date
JPS62108577A (ja) 1987-05-19

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