JPS61146977U - - Google Patents

Info

Publication number
JPS61146977U
JPS61146977U JP1985030424U JP3042485U JPS61146977U JP S61146977 U JPS61146977 U JP S61146977U JP 1985030424 U JP1985030424 U JP 1985030424U JP 3042485 U JP3042485 U JP 3042485U JP S61146977 U JPS61146977 U JP S61146977U
Authority
JP
Japan
Prior art keywords
recess
circuit
hybrid integrated
integrated circuit
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985030424U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985030424U priority Critical patent/JPS61146977U/ja
Publication of JPS61146977U publication Critical patent/JPS61146977U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Description

【図面の簡単な説明】
第1図はこの考案による混成集積回路装置の実
施例を示す断面図、第2図は従来の混成集積回路
装置の例を示す断面図である。 図において、1は基板、2は導体、3は部品用
電極、4は回路部品、5は導電性接着剤、6はワ
イヤ、7は絶縁体である。なお、各図中同一符号
は同一又は相当部分を示す。

Claims (1)

    【実用新案登録請求の範囲】
  1. 回路部品を搭載して電子回路を構成する混成集
    積回路装置において、サブストレートを形成する
    基板の上記回路部品を搭載する部分の周囲を絶縁
    体により段状に高くして回路部品搭載部分を相対
    的に凹部とし、この凹部内を回路部品を導電性接
    着剤で固着してあることを特徴とする混成集積回
    路装置。
JP1985030424U 1985-03-04 1985-03-04 Pending JPS61146977U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985030424U JPS61146977U (ja) 1985-03-04 1985-03-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985030424U JPS61146977U (ja) 1985-03-04 1985-03-04

Publications (1)

Publication Number Publication Date
JPS61146977U true JPS61146977U (ja) 1986-09-10

Family

ID=30530110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985030424U Pending JPS61146977U (ja) 1985-03-04 1985-03-04

Country Status (1)

Country Link
JP (1) JPS61146977U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10270589A (ja) * 1997-03-25 1998-10-09 Rohm Co Ltd 半導体装置の構造

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10270589A (ja) * 1997-03-25 1998-10-09 Rohm Co Ltd 半導体装置の構造

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