JPS61156239U - - Google Patents

Info

Publication number
JPS61156239U
JPS61156239U JP3818885U JP3818885U JPS61156239U JP S61156239 U JPS61156239 U JP S61156239U JP 3818885 U JP3818885 U JP 3818885U JP 3818885 U JP3818885 U JP 3818885U JP S61156239 U JPS61156239 U JP S61156239U
Authority
JP
Japan
Prior art keywords
substrate
integrated circuit
circuit chip
light shielding
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3818885U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3818885U priority Critical patent/JPS61156239U/ja
Publication of JPS61156239U publication Critical patent/JPS61156239U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Description

【図面の簡単な説明】
第1図は本考案に係る集積回路チツプの遮光構
造を示す断面図、第2図は第1図のL矢視裏面図
、第3図は従来の集積回路チツプの装着構造を示
す断面図である。 11……集積回路チツプ、12……電極端子、
14……導体パターン、15……基板、16……
金属粉、17……異方性導電接着剤、18……遮
蔽パターン。

Claims (1)

    【実用新案登録請求の範囲】
  1. 光透過性の基板と、この基板上に導電体により
    形成された配線パターンと、この配線パターンに
    接続される電極端子を有し前記基板上に配設され
    る集積回路チツプと、この集積回路チツプが配設
    される位置に対応して前記基板上に設けた遮光部
    材とを具備する集積回路チツプの遮光構造。
JP3818885U 1985-03-19 1985-03-19 Pending JPS61156239U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3818885U JPS61156239U (ja) 1985-03-19 1985-03-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3818885U JPS61156239U (ja) 1985-03-19 1985-03-19

Publications (1)

Publication Number Publication Date
JPS61156239U true JPS61156239U (ja) 1986-09-27

Family

ID=30544958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3818885U Pending JPS61156239U (ja) 1985-03-19 1985-03-19

Country Status (1)

Country Link
JP (1) JPS61156239U (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000002244A1 (fr) * 1998-07-01 2000-01-13 Seiko Epson Corporation Dispositif a semi-conducteur, procede de fabrication associe, carte imprimee et dispositif electronique
JP2003023035A (ja) * 2001-07-05 2003-01-24 Sharp Corp 半導体装置
KR100498848B1 (ko) * 1998-12-21 2005-07-04 세이코 엡슨 가부시키가이샤 회로 기판 및 회로 기판을 사용한 표시 장치 및 전자 기기

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000002244A1 (fr) * 1998-07-01 2000-01-13 Seiko Epson Corporation Dispositif a semi-conducteur, procede de fabrication associe, carte imprimee et dispositif electronique
KR100498848B1 (ko) * 1998-12-21 2005-07-04 세이코 엡슨 가부시키가이샤 회로 기판 및 회로 기판을 사용한 표시 장치 및 전자 기기
JP2003023035A (ja) * 2001-07-05 2003-01-24 Sharp Corp 半導体装置

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