JP2000091376A - 電子回路装置 - Google Patents

電子回路装置

Info

Publication number
JP2000091376A
JP2000091376A JP10276547A JP27654798A JP2000091376A JP 2000091376 A JP2000091376 A JP 2000091376A JP 10276547 A JP10276547 A JP 10276547A JP 27654798 A JP27654798 A JP 27654798A JP 2000091376 A JP2000091376 A JP 2000091376A
Authority
JP
Japan
Prior art keywords
conductor layer
main surface
electrode
electronic
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10276547A
Other languages
English (en)
Inventor
Masaki Naganuma
正樹 長沼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP10276547A priority Critical patent/JP2000091376A/ja
Publication of JP2000091376A publication Critical patent/JP2000091376A/ja
Withdrawn legal-status Critical Current

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Abstract

(57)【要約】 【課題】 高周波電力増幅器においてＦＥＴのソースの
配線の寄生インダクタンスが大きくなり、高周波特性が
悪化した。 【解決手段】 回路基板２のグランド導体層１０の上に
ＦＥＴ１を固着する。ＦＥＴ１の上面９のソース電極４
を導電性ペーストに基づいて形成された接続導体層１６
によって回路基板２のグランド導体層１０に接続する。
ドレイン電極５及びゲート電極６はワイヤ１７、１８で
回路基板２上の導体層１１、１２に接続する。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は携帯電話の高周波電
力増幅器等の電子回路装置に関する。
【０００２】
【従来の技術】高周波電力増幅器は、回路基板上に例え
ばＦＥＴ（電界効果トランジスタ）を固着し、ソース電
極、ドレイン電極、ゲート電極をワイヤによって回路基
板上の導体層即ちパッドに接続することにより構成され
ている。
【０００３】
【発明が解決しようとする課題】ところで、高周波電子
回路装置においては、寄生インダクタンスによる特性悪
化が問題になる。例えば、上記のＦＥＴを使用した高周
波増幅器において、ソース電極と回路基板上の導体層と
の間をワイヤで接続すると、ワイヤの寄生インダクタン
スによる周波数特性の悪化が生じる。
【０００４】そこで、本発明の目的は、寄生インダクタ
ンスの低減を図ることができる電子回路装置を提供する
ことにある。
【０００５】
【課題を解決するための手段】上記課題を解決し、上記
目的を達成するための本発明は、電子素子の第１の主面
が回路基板上に固着され、前記電子素子の前記第１の主
面に対向する第２の主面に少なくとも１つの電極が形成
されている電子回路装置であって、前記電子素子の前記
第２の主面の前記少なくとも１つの電極と前記回路基板
の導体層とを電気的に接続するように前記電子素子の前
記第２の主面の一部及び前記電子素子の側面の一部に沿
うように接続導体層が形成され、前記接続導体層はペー
スト状の導電性接合材を塗布して固化させたものから成
ることを特徴とする電子回路装置に係わるものである。
なお、請求項２に示すようにワイヤによる接続とペース
ト状導電性接合材による接続との組み合せ構造にするこ
とが望ましい。
【０００６】
【発明の効果】各請求項の発明によれば、電子素子の第
２の主面（上面）の少なくとも１つの電極がワイヤによ
って回路基板の導体層に接続されないで、導電性ペース
トに基づいて接続される。導電性ペーストに基づく接続
導体層は電子素子の側面に沿って形成されるので、この
全長は従来のワイヤによる接続に比べて短くなり、且つ
細線（ワイヤ）に比べて断面積が大きくなり、寄生イン
ダクタンスが低減する。また、請求項２の発明によれ
ば、導電性ペーストによる接続とワイヤによる接続の組
み合せによって合理性の高い接続を達成することができ
る。
【０００７】
【実施形態及び実施例】次に、図１〜図４を参照して本
発明の実施形態及び実施例を説明する。
【０００８】
【第１の実施例】本発明の第１の実施例の電子回路装置
は、ＦＥＴを使用した高周波電力増幅器であって、図１
に示すＦＥＴ１を図２及び図３に示すように回路基板２
に取付けたものである。なお、回路基板２には駆動回
路、整合回路等が設けられるが、図２及び図３では省略
されている。
【０００９】ＦＥＴ１は、半導体基体３とソース電極４
とドレイン電極５とゲート電極６と絶縁膜７とから成
る。半導体基体３は互いに対向している第１の主面（下
面）８と第２の主面（上面）９とを有し、両主面８、９
間には図示が省略されている周知のソース領域、ボディ
領域（チャネル形成領域）及びドレイン領域が設けられ
ている。絶縁膜７は半導体基体９の第２の主面９上に形
成されている。ソース電極４及びドレイン電極５は絶縁
膜７上に形成され、絶縁膜７の孔を介して半導体基体３
のソース領域及びドレイン領域に接続されている。ゲー
ト電極６は半導体基体３上の周知のゲート絶縁膜（図示
せず）の上に形成されている。ＦＥＴ１の構成を更に詳
しく説明すると、ソース領域とドレイン領域とボディ領
域は半導体基体３の第２の主面９に露出するように配置
され、島状に形成されたソース領域とドレイン領域には
ソース電極４とドレイン電極５とが接続され、ソース領
域とドレイン領域との相互間のボディ領域（チャネル形
成領域）の上にはゲート絶縁膜を介してゲート電極６が
設けられている。なお、本実施例のＦＥＴ１は複数の微
小ＦＥＴ（セル）を並列接続された構造に形成されてい
る。
【００１０】回路基板２はセラミック又は樹脂又はガラ
ス入れ樹脂から成る絶縁性基板であって、この表面にグ
ランド導体層１０と、ドレイン接続導体層１１と、ゲー
ト接続導体層１２とが設けられている。
【００１１】ＦＥＴ１の一方の主面即ち半導体基体３の
第１の主面８は接着層１３によってグランド導体層１０
に固着されている。ＦＥＴ１即ち半導体基体３の第２の
主面９上の一部及び側面１４の一部に沿うようにソース
電極４とグランド導体層１０とを接続する４つの接続導
体層１６が形成されている。接続導体層１６は導電性ペ
ースト（例えば導電性粒子入れ樹脂から成るペースト状
導電性接着剤又は銀粒子と有機バインダと無機バインダ
と溶剤とから成るペースト）を塗布して固化したもので
ある。半導体基体３の上面は絶縁膜７によって接続導体
層１６と分離されている。なお、半導体基体３は側面に
沿って分離領域を有し、内部の能動領域は分離領域によ
って外部から電気的に分離されている。従って、半導体
基体３の側面に接続導体層１６を形成することが可能で
ある。
【００１２】ワイヤ接続用電極としてのドレイン電極５
とドレイン接続用導体層１１は金属細線から成る複数の
ワイヤ１７によって接続されている。また、ワイヤ接続
用電極としてのゲート電極６とゲート接続用導体層１２
との間もワイヤ１８によって接続されている。ワイヤ１
７、１８による接続は周知のワイヤボンディング方法に
よって行われている。
【００１３】上述から明らかなようにソース電極４とソ
ース接続導体層としてのグランド導体層１０との間はワ
イヤによって接続されないで、導電性ペーストに基づく
接続導体層１６によって接続されている。この接続導体
層１６はＦＥＴ１の側面に沿うように配置されるので、
この全長は従来のワイヤで接続する場合に比べて短くな
り、且つこの断面積がワイヤよりも大きくなり、エミッ
タ電極４とグランド導体層１０との間の寄生インダクタ
ンスが小さくなり、増幅器の高周波特性が向上する。ま
た、接続導体層１６とワイヤ１７、１８との組み合せに
よって複数の電極４、５、６の接続を容易に達成するこ
とができる。
【００１４】
【変形例】本発明は上述の実施例に限定されるものでは
なく、例えば次の変形が可能なものである。 （１） ＦＥＴ１の代りにバイポーラトランジスタの増
幅器等にも本発明を適用することができる。 （２） 回路基板２を多層基板にすることができる。 （３） ＦＥＴ１の側面に絶縁層を設け、この上に導電
性ペ−ストによって接続導体層１６を形成することがで
きる。 （４） 半導体基体３の第１の主面側に金属層を設け、
これを基板２の導体層に半田又はろう材で固着すること
ができる。
【図面の簡単な説明】
【図１】本発明の第１の実施例に係わるＦＥＴを示す平
面図である。
【図２】本発明の第１の実施例の電子回路装置を図３の
Ａ−Ａ線に相当する部分で示す断面図である。
【図３】図２の電子回路装置の平面図である。
【符号の説明】
１ ＦＥＴ ２ 回路基板 ３ 半導体基体 ４ ソース電極 ５ ドレイン電極 ６ ゲート電極 １０ グランド導体層 １６ 接続導体層

Claims (2)

    【特許請求の範囲】
  1. 【請求項１】 電子素子の第１の主面が回路基板上に固
    着され、前記電子素子の前記第１の主面に対向する第２
    の主面に少なくとも１つの電極が形成されている電子回
    路装置であって、 前記電子素子の前記第２の主面の前記少なくとも１つの
    電極と前記回路基板の導体層とを電気的に接続するよう
    に前記電子素子の前記第２の主面の一部及び前記電子素
    子の側面の一部に沿うように接続導体層が形成され、 前記接続導体層はペースト状の導電性接合材を塗布して
    固化させたものから成ることを特徴とする電子回路装
    置。
  2. 【請求項２】 前記電子素子は、更に、前記第２の主面
    にワイヤ接続用電極を有し、前記回路基板は更にワイヤ
    接続導体層を有し、前記ワイヤ接続用電極と前記ワイヤ
    接続導体層とがワイヤで接続されていることを特徴とす
    る請求項１記載の電子回路装置。
JP10276547A 1998-09-11 1998-09-11 電子回路装置 Withdrawn JP2000091376A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10276547A JP2000091376A (ja) 1998-09-11 1998-09-11 電子回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10276547A JP2000091376A (ja) 1998-09-11 1998-09-11 電子回路装置

Publications (1)

Publication Number Publication Date
JP2000091376A true JP2000091376A (ja) 2000-03-31

Family

ID=17571014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10276547A Withdrawn JP2000091376A (ja) 1998-09-11 1998-09-11 電子回路装置

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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173214A (ja) * 2004-12-14 2006-06-29 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2007123884A (ja) * 2005-10-26 2007-05-17 General Electric Co <Ge> 電力回路パッケージ及びその製作方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173214A (ja) * 2004-12-14 2006-06-29 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP4619104B2 (ja) * 2004-12-14 2011-01-26 パナソニック株式会社 半導体装置
JP2007123884A (ja) * 2005-10-26 2007-05-17 General Electric Co <Ge> 電力回路パッケージ及びその製作方法

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