JPS6197861U - - Google Patents

Info

Publication number
JPS6197861U
JPS6197861U JP18353584U JP18353584U JPS6197861U JP S6197861 U JPS6197861 U JP S6197861U JP 18353584 U JP18353584 U JP 18353584U JP 18353584 U JP18353584 U JP 18353584U JP S6197861 U JPS6197861 U JP S6197861U
Authority
JP
Japan
Prior art keywords
channel width
width
semiconductor device
active region
mos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18353584U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18353584U priority Critical patent/JPS6197861U/ja
Publication of JPS6197861U publication Critical patent/JPS6197861U/ja
Pending legal-status Critical Current

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Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案に係る半導体装置をＭＯＳ Ｌ
ＳＩに適用した一実施例を示す平面図、第２図は
ＭＯＳ ＦＥＴを示す平面図、第３図はＭＯＳ
ＦＥＴのチヤネル幅Ｗとゲート幅Ｌとの関係を示
すグラフ、第４図は従来のＭＯＳ ＬＳＩを示す
平面図である。 なお図面に用いた符号において、１，４…多結
晶シリコンゲート、５，６，８…ＭＯＳ ＦＥＴ
、１１ａ〜１１ｃ…活性領域、である。

Claims (1)

    【実用新案登録請求の範囲】
  1. チヤンネル幅Ｗ１の活性領域を有する第１のＭ
    ＯＳトランジスタと、チヤネル幅Ｗ２（但し、Ｗ
    ２〉Ｗ１）の活性領域を有する第２のＭＯＳトラ
    ンジスタとが同一基板上に設けられている半導体
    装置において、上記第２のＭＯＳトランジスタの
    上記チヤンネル幅Ｗ２の活性領域が、互いにほぼ
    同一の幅を有しかつ上記チヤネル幅Ｗ１に対する
    それぞれの幅の比がほぼ１に等しい複数の活性領
    域に分割して設けられていることを特徴とする半
    導体装置。
JP18353584U 1984-12-03 1984-12-03 Pending JPS6197861U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18353584U JPS6197861U (ja) 1984-12-03 1984-12-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18353584U JPS6197861U (ja) 1984-12-03 1984-12-03

Publications (1)

Publication Number Publication Date
JPS6197861U true JPS6197861U (ja) 1986-06-23

Family

ID=30741029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18353584U Pending JPS6197861U (ja) 1984-12-03 1984-12-03

Country Status (1)

Country Link
JP (1) JPS6197861U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04132253A (ja) * 1990-09-25 1992-05-06 Nec Corp 出力回路
JP2006060156A (ja) * 2004-08-24 2006-03-02 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5333072A (en) * 1976-09-09 1978-03-28 Nec Corp Semiconductor device
JPS6037158A (ja) * 1983-08-08 1985-02-26 Nec Ic Microcomput Syst Ltd Ｍｏｓ型集積回路
JPS6037159A (ja) * 1983-08-08 1985-02-26 Nec Ic Microcomput Syst Ltd Ｍｏｓ型集積回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5333072A (en) * 1976-09-09 1978-03-28 Nec Corp Semiconductor device
JPS6037158A (ja) * 1983-08-08 1985-02-26 Nec Ic Microcomput Syst Ltd Ｍｏｓ型集積回路
JPS6037159A (ja) * 1983-08-08 1985-02-26 Nec Ic Microcomput Syst Ltd Ｍｏｓ型集積回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04132253A (ja) * 1990-09-25 1992-05-06 Nec Corp 出力回路
JP2006060156A (ja) * 2004-08-24 2006-03-02 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法

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