JPS61232646A - 樹脂封止型半導体集積回路装置 - Google Patents

樹脂封止型半導体集積回路装置

Info

Publication number
JPS61232646A
JPS61232646A JP7481885A JP7481885A JPS61232646A JP S61232646 A JPS61232646 A JP S61232646A JP 7481885 A JP7481885 A JP 7481885A JP 7481885 A JP7481885 A JP 7481885A JP S61232646 A JPS61232646 A JP S61232646A
Authority
JP
Japan
Prior art keywords
layer
protective layer
region
resin
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7481885A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0415626B2 (enrdf_load_stackoverflow
Inventor
Takeshi Okazawa
武 岡澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7481885A priority Critical patent/JPS61232646A/ja
Publication of JPS61232646A publication Critical patent/JPS61232646A/ja
Publication of JPH0415626B2 publication Critical patent/JPH0415626B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP7481885A 1985-04-09 1985-04-09 樹脂封止型半導体集積回路装置 Granted JPS61232646A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7481885A JPS61232646A (ja) 1985-04-09 1985-04-09 樹脂封止型半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7481885A JPS61232646A (ja) 1985-04-09 1985-04-09 樹脂封止型半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS61232646A true JPS61232646A (ja) 1986-10-16
JPH0415626B2 JPH0415626B2 (enrdf_load_stackoverflow) 1992-03-18

Family

ID=13558272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7481885A Granted JPS61232646A (ja) 1985-04-09 1985-04-09 樹脂封止型半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS61232646A (enrdf_load_stackoverflow)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2625839A1 (fr) * 1988-01-13 1989-07-13 Sgs Thomson Microelectronics Procede de passivation d'un circuit integre
US5627403A (en) * 1993-05-31 1997-05-06 Sgs-Thomson Microelectronics S.R.L. Adhesion between dielectric layers in an integrated circuit
US5633534A (en) * 1993-12-06 1997-05-27 Sgs-Thomson Microelectronics, Inc. Integrated circuit with enhanced planarization
US5793114A (en) * 1993-12-17 1998-08-11 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6051864A (en) * 1993-12-17 2000-04-18 Stmicroelectronics, Inc. Memory masking for periphery salicidation of active regions
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723229A (en) * 1980-07-17 1982-02-06 Toshiba Corp Semiconductor device and its manufacture
JPS57104532U (enrdf_load_stackoverflow) * 1980-12-16 1982-06-28

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723229A (en) * 1980-07-17 1982-02-06 Toshiba Corp Semiconductor device and its manufacture
JPS57104532U (enrdf_load_stackoverflow) * 1980-12-16 1982-06-28

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01225326A (ja) * 1988-01-13 1989-09-08 Sgs Thomson Microelectron Sa 集積回路のパッシベーション方法
FR2625839A1 (fr) * 1988-01-13 1989-07-13 Sgs Thomson Microelectronics Procede de passivation d'un circuit integre
US5795821A (en) * 1993-05-31 1998-08-18 Sgs-Thomson Microelectronics, S.R.L. Process for improving the interface union among dielectric materials in an integrated circuit manufacture
US5627403A (en) * 1993-05-31 1997-05-06 Sgs-Thomson Microelectronics S.R.L. Adhesion between dielectric layers in an integrated circuit
US5837613A (en) * 1993-12-06 1998-11-17 Stmicroelectronics, Inc. Enhanced planarization technique for an integrated circuit
US5633534A (en) * 1993-12-06 1997-05-27 Sgs-Thomson Microelectronics, Inc. Integrated circuit with enhanced planarization
US5986330A (en) * 1993-12-06 1999-11-16 Stmicroelectronics, Inc. Enhanced planarization technique for an integrated circuit
USRE39690E1 (en) * 1993-12-06 2007-06-12 Stmicroelectronics, Inc. Enhanced planarization technique for an integrated circuit
US5793114A (en) * 1993-12-17 1998-08-11 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6051864A (en) * 1993-12-17 2000-04-18 Stmicroelectronics, Inc. Memory masking for periphery salicidation of active regions
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US6284584B1 (en) * 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
US6514811B2 (en) 1993-12-17 2003-02-04 Stmicroelectronics, Inc. Method for memory masking for periphery salicidation of active regions
US6661064B2 (en) 1993-12-17 2003-12-09 Stmicroelectronics, Inc. Memory masking for periphery salicidation of active regions

Also Published As

Publication number Publication date
JPH0415626B2 (enrdf_load_stackoverflow) 1992-03-18

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