JPS61198356A - マルチプロセツサ・システム - Google Patents

マルチプロセツサ・システム

Info

Publication number
JPS61198356A
JPS61198356A JP3998885A JP3998885A JPS61198356A JP S61198356 A JPS61198356 A JP S61198356A JP 3998885 A JP3998885 A JP 3998885A JP 3998885 A JP3998885 A JP 3998885A JP S61198356 A JPS61198356 A JP S61198356A
Authority
JP
Japan
Prior art keywords
signal
cpu
main cpu
chip
general
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3998885A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0215095B2 (enrdf_load_stackoverflow
Inventor
Kenji Hara
憲二 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaskawa Electric Corp
Original Assignee
Yaskawa Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaskawa Electric Manufacturing Co Ltd filed Critical Yaskawa Electric Manufacturing Co Ltd
Priority to JP3998885A priority Critical patent/JPS61198356A/ja
Publication of JPS61198356A publication Critical patent/JPS61198356A/ja
Publication of JPH0215095B2 publication Critical patent/JPH0215095B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP3998885A 1985-02-27 1985-02-27 マルチプロセツサ・システム Granted JPS61198356A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3998885A JPS61198356A (ja) 1985-02-27 1985-02-27 マルチプロセツサ・システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3998885A JPS61198356A (ja) 1985-02-27 1985-02-27 マルチプロセツサ・システム

Publications (2)

Publication Number Publication Date
JPS61198356A true JPS61198356A (ja) 1986-09-02
JPH0215095B2 JPH0215095B2 (enrdf_load_stackoverflow) 1990-04-11

Family

ID=12568320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3998885A Granted JPS61198356A (ja) 1985-02-27 1985-02-27 マルチプロセツサ・システム

Country Status (1)

Country Link
JP (1) JPS61198356A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0215095B2 (enrdf_load_stackoverflow) 1990-04-11

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