JPS61198356A - Multi-processor system - Google Patents

Abstract

PURPOSE:To prevent reduction in the execution speed with less number of components by generating a DMA request signal just before when one-chip CPU accesses a RAM of a main CPU and using a signal replying DMA enable from the main CPU so as to switch a bus. CONSTITUTION:A read or a write signal from the one-chip CPU is inputted and an HOLD signal with a prescribed width is generated after a prescribed time. When the one-chip CPU 1 sends the read signal RD or write signal WR, a monostable multivibrator 4a gives a delay of 6.5musec and a monostable multi-vibrator 4b sends a pulse of 2musec width. The pulse becomes the HOLD signal, which is sent to the main CPU. When the main CPU receives the HOLD signal, an HLDA signal being its reply is sent to a bus buffer to open the bus buffer 2, and the read signal RD or the write signal WR stopped by the bus buffer 2 is given to the main CPU as an MRD or an MWR respectively and the one- chip CPU 1 can access directly the data of the RAM used by the main CPU.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention uses a main dPU as a general-purpose CPU, and a sub-CPU as a general-purpose CPU.
The present invention relates to a multiprocessor system using a single-chip CPU having an external memory access function.

[Prior art j] In such a system, a general-purpose CPU and a one-chip C
It is necessary to configure the PU so that it does not access the external memory (hereinafter referred to as AM) at the same time.

For example, from the RAM FFQQli address, ■chip C
A case will be described in which 16 bytes of data are transferred (ie, RAM data is read) to address '30H' in the internal memory of the PU.

First, if a program is created ignoring the general-purpose CPU, the program shown in FIG. 3 can be considered.

However, in reality, a general-purpose CPU may access RAM, so when a chip CPU executes a RAM access-through instruction (MOVX A, @DPTR), it is necessary to establish bus occupancy for one chip CPU. be.

In response to this, the applicant has previously filed a patent application filed in 1973.
8-91454 is proposed.

This proposal is based on the summer chip CPU, general-purpose CPU, as shown in Figure 4.
A common bus is directly connected between the PU and external memory, and when processing data, the general-purpose CPU is made to occupy the bus and perform data processing, and when transferring data, the general-purpose CPU
The chip CPU issues a HOLD request to the general-purpose CPU to cause the general-purpose CPU to relinquish the bus, and the single-chip CPU occupies the bus.

However, in such a system, the general-purpose CPU that is temporarily inactive remains in the HOLD state, so
It has become clear that when the number of bytes of data transfer is large, the execution time decreases significantly, resulting in inefficient processing.

Therefore, Japanese Patent Application No. 58-177715 was proposed for the purpose of providing a multiprocessor system capable of eliminating the above-mentioned drawbacks and preventing a decrease in CPU execution speed.

The gist of this proposal is that, as shown in FIG. (determined by the program to be executed), the general-purpose CPU issues a WAIT signal to prevent it from accessing the RAM, then disconnects the bus connecting the general-purpose CPU and the RAM, and occupies the RAM for the time required for the l-chip CPU to access it. The point was to make it possible.

[Intersection point J that the invention seeks to solve However, although the number of parts is small in Japanese Patent Application No. 58-91454, the execution speed of the main CPU decreases too much, and in Japanese Patent Application No. 58-177715, the execution speed does not decrease. The problem was that there were too many parts.

The present invention has been made to solve these problems, and it is an object of the present invention to provide a system that uses fewer parts and does not cause a decrease in execution speed.

[Means for Solving the Problems J] Therefore, the present invention provides a system in which one chip CPU is the main CPU.
A simple hardware circuit is provided that issues a DMA request signal just before accessing M, and switches the bus in response to a DMA response signal from the computer/cPU.

[Effect]

The simple hardware circuit described above has the function of inputting a read signal or a write signal generated by a 1.1-chip CPU, and outputting a HOLD signal of a predetermined width after a predetermined time.

〔Example〕

Hereinafter, a specific embodiment of the present invention will be described with reference to FIG. 1 and its time chart shown in FIG. 2.

■ is a l-chip CP that can access external data memory
Here, Intel 8051 is an example.

The main CPU (not shown) is, for example, the company's 8088.

2 is a bus buffer, 3 is an NO gate, and 4a and 4b are monostable multivibrators (hereinafter abbreviated as monomulti).

The monomultis 4a and 4b are each connected to a resistor and a capacitor, and by adjusting the resistance value of the resistor, 4a works as a 6.5 μsec timing delayer, and 4b works as a 2 μsec width pulse sender. .

Now, when the 1-chip CPUI sends out the read signal fI5 or the write signal WI, the monomulti 4a delays it by 6.5 μs as shown in FIG.
Sends out microsecond-wide pulses.

This pulse becomes the HOLD signal, and the main C (not shown)
Sent to PU.

Since the main CPU (Intel 8088) operates in 4T cycles, if the reference clock is 3M [(z), it takes a maximum of 0.5 μs to accept this HOLD signal.

(°, -1÷(8X/O6)X4=O15X/O-6)
Therefore, in the above-mentioned Japanese Patent Application No. 177,715/1984, the delay was set at 7 .mu. seconds, but the delay was increased by 0.5 .mu. seconds to 6.5 seconds.

Further, since reading or writing requires 1 .mu.sec, the HOLD signal width is set to 2 .mu.sec to provide a margin, which is the same idea as the above-mentioned Japanese Patent Application No. 58-177715. (However, in the patent application No. 58-177715, the HOLD signal is not used (WA
IT signal) When the main CPU receives this HOLD signal, it issues the HLDA signal as a response to the pass buffer to open the pass buffer 2, and sends the read signal πl or write signal WR, which was stopped by the pass buffer 12, to the MRD and MRD, respectively. By passing it to the main CPU as MWR, the 1-chip CPU 1 can directly access the ELAM data used by the main CPU.

Regarding the transfer algorithm, please refer to the patent application No. 58-1777.
Since it is the same as 15, it is omitted here.

Here, the advantages of the present invention will be described in the above-mentioned Japanese Patent Application No. 58-91454.
, compared with Japanese Patent Application No. 58-177715, the dead time of the main CPU for 16-byte transfer is 128 μs and 0-16 μs (varies depending on the time of signal reception) in the two applications, while in this case In the invention, 32 μs ('
,' 2 microseconds x 16 bytes = 32).

Although the present invention is slightly inferior to the dead time of Japanese Patent Application No. 58-177715, it requires very few additional parts and is inexpensive, so its economic value is very high (and practical).

[Other Examples]

In this embodiment, the timing delay function was realized using two monomultis, but a counter may be used to count clocks and generate timing.

Also, 1-chip CPU is not limited to 8051, but 8031
．． Of course, 8751 or the like is also fine.

〔Effect of the invention〕

As described above, the present invention has the great effect of being able to provide an efficient one-chip CPU system with the addition of only a few components.

[Brief explanation of the drawing]

FIG. 1 shows a specific embodiment of the present invention, FIG. 2 shows a time chart of the invention, FIG. 3 shows a conventional program, and FIGS. 4 and 5 show an example of a conventional one-chip CPU system. [1 chip CPU, 2: pass buffer 1.3: NOR gate, 4a, 4b = monostable multivibrator Patent applicant Yaskawa Electric Co., Ltd. Figure 1 Figure 2 Figure 3 (2-Monitor) (Processing time: MC) (t
Taste) Figure 4 Figure 5

Claims (1)

[Claims] A general-purpose CPU with a HOLD function and a 1-chip CPU with an external memory access function via an I/O port.
A bus is directly connected between them, and when processing data, the general-purpose CPU occupies the bus and processes the data, and when transferring data, the one-chip CPU connects the general-purpose CPU to the general-purpose CPU. On the other hand, HOL
In a multiprocessor system in which the general-purpose CPU occupies a bus by issuing a D request, a read signal or a write signal issued by the one-chip CPU is input and delayed by a predetermined time to generate a HOL of a predetermined width.
A multiprocessor system characterized by comprising a circuit that issues a D request signal.