JPH04101261A - Information processing device - Google Patents

Abstract

PURPOSE:To obtain an information processing device which can maintain software interchangeability by providing a timing control circuit which detects continuous access to an input-output device and a ready control circuit which outputs a control signal for terminating the access to a master device in accordance with the content of the timing control circuit. CONSTITUTION:Latch circuits 1 and 2 supply addresses and data from a system bus to an I/O bus 5 separated from the system bus in accordance with the latch timing from a timing control circuit 3 after tentatively storing the addresses and data. The circuit 3, on the other hand, outputs control signals to each I/O (1-1)-(1-n) at required timing while the circuit 3 detects continuous access to the same I/O from the output of an address decoder 6. A ready control circuit 4 supplies a ready signal for terminating the access to a master device 7 in accordance with the signal of the circuit 3. Therefore, the recovery time of the I/Os can be secured by detecting the access to the I/Os and software interchangeability can be maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device having an input/output device (hereinafter referred to as I/O) with a slow processing speed as a component.

[Conventional technology]

In this type of information processing apparatus, the master device is
When writing data to lo, it takes a long time and reduces the processing capacity of the master device. Same Il again
When continuously accessing Ilo, the software had to be aware of guaranteeing Ilo recovery time.

Conventionally, as a countermeasure of this type, a technique has been adopted in which a self-jump instruction or the like is inserted between successive accesses to guarantee the recovery time.

FIG. 3 is a block diagram showing one such conventional example, and FIG. 4 is a waveform diagram thereof.

In FIG. 3, the master device 11 is l/O1-1
, I/01-2, -I/01-n, the wait circuit 9 extends the access until data writing to Ilo is completed. As shown in Figure 4, in the factory/O access 1,
The master device 11 is made to wait until tl2 when data writing to lo ends, and the generation of I/O access 2, which is continuous access to the same Ilo, is controlled by software. In other words, Ntl. The software guarantees the glue recovery time from t□3 to t□3.

[Problem to be solved by the invention]

In the conventional information processing apparatus described above, when the master device writes data to each I/O, the processing speed of Ilo is very slow, so the master device is forced to wait for the access to complete, which significantly reduces processing power. It was intended to reduce the Also, in software, continuous same I
Accessing Ilo has the drawback that a recovery time must be guaranteed so that the next access is not made in a state where the operation of Ilo has not been completely completed with respect to the previous access.

An object of the present invention is to improve the above-mentioned drawbacks, and when a master device writes data to each I/O, it temporarily stores the address and data, terminates the master device's access, and then writes the data to Ilo at a required timing. It improves the processing capacity of the master device by writing
An object of the present invention is to provide an information processing device that can maintain software compatibility by guaranteeing the recovery time by hardware even in consecutive accesses to the same Ilo.

[Means to solve the problem]

The information processing device of the present invention has an I/O bus to which a plurality of input/output devices with low processing speeds are connected, which is separated from other buses, and an address and an address when a master device writes data to the input/output device. A latch circuit that temporarily stores data and supplies it to the I/O bus, a latch timing for the latch circuit, a control signal to each input/output device, a timing control circuit that detects continuous access to the same input/output device, and a timing control circuit. and a ready control circuit that outputs a control signal to terminate access of the master device depending on the contents of the circuit.

〔Example〕

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining its operation.

In FIG. 1, latch circuit 1. The latch circuit 2 has the role of temporarily storing the address and data from the system bus according to the latch timing from the timing control circuit 3, and supplying the data to the I/O bus 5 separated from the system bus.

On the other hand, the timing control circuit 3 outputs a control signal to each I/O at a required timing while detecting successive accesses to the same Ilo from the output of the address decoder 6. Also, in the ready control circuit 4, the master device (CPU, DMAC, etc.) 7 is controlled by the signal from the timing control circuit 3.
This shows that a ready signal is supplied to terminate the access to.

The signal waveform at this time is as shown in Figure 2. When writing data in I/O access 1, the address (a) and data (c) from the master device 7 are latched at tl, and t2
Terminate the access of master device 7 with Ready
At the same time as outputting (f), data (
Output WR(e) to write d). Therefore, since access by the master device 7 has been completed at j2, other processing can be executed from t2.

In addition, the timing control circuit 3 starts counting clocks in order to guarantee recovery time for continuous access to the same Ilo.
For example, if the target Ilo needs to guarantee recovery time until t5, even if I/O access 2, which is an I/O access to the same Ilo, occurs from t3, latch circuit 1 and latch circuit 2 should not be The ready control circuit 4 inserts a wait cycle into the master device without outputting the latch timing.

Then, at t5 when the recovery time is guaranteed, the latch circuit 1. Outputs the latch timing to the latch circuit 2, latches the address (a) and data (c), and t6
At the same time, ReadV (f) is output to the master device 7 to end the access, and at the same time, WR (e) is output to the actual Ilo and data (d) is written.

〔Effect of the invention〕

According to the present invention, when the master device writes data to Ilo, the access can be quickly completed without being affected by Ilo, which has a slow processing speed, so that the processing capacity of the master device can be improved. Further, by detecting successive accesses to the same Ilo using hardware and guaranteeing a recovery time, software compatibility is maintained.

Claims (1)

[Claims] An I/O bus to which multiple input/output devices with low processing speeds are connected and which are separated from other buses; A latch circuit that temporarily stores data and supplies it to the I/O bus; A timing control circuit that detects latch timing for the latch circuit, control signals to each input/output device, and continuous access to the same input/output device; An information processing apparatus comprising: a ready control circuit that outputs a control signal for terminating access by a master device depending on the content.