JPH04119448A - Operation timing control system - Google Patents

Abstract

PURPOSE:To connect a processor and a peripheral interface which are different in operation timing by sending a control signal, which is set by a chip select signal and is reset by a data transfer acknowledge signal and stops the operation of the processing in the period of setting, to adjust the operation timing. CONSTITUTION:A processor operation control means 15 stops the operation of a processor 11 by the chip select signal, which the processor sends at the time of accessing a peripheral interface 13, to delay data and the address. Meanwhile, the peripheral interface 13 takes in data during this delay to send the data transfer acknowledge signal because being operated by a clock independent of the processor 11. The processor operation control means 15 releases the operation stop state of the processor 11 by the data transfer acknowledge signal sent from the peripheral interface 13. Thus, data is transferred between the processor and the peripheral interface different in operation timing.

Description

[Detailed Description of the Invention] [Summary] This invention relates to an operation timing control method between processors and peripheral interfaces that have different operation timings. A processor having a control terminal that stops operation upon input of a control signal, and a peripheral interface that operates with a faster clock than the operating clock of this processor and outputs a data transfer acknowledge signal in response to data acquisition. In the operation timing control method, it is set by the chip select signal sent from the processor when accessing the peripheral interface, is reset by the data transfer acknowledge signal, and during the setting, the control signal that stops the processor operation is sent to control the operation timing. The processor operation control unit is configured to include processor operation control means for adjusting.

[Industrial application field]

The present invention relates to an operation timing control method between a processor and a peripheral interface, which have different operation timings, in a panel equipped with a peripheral interface that accommodates a processor, memory, and peripheral devices.

Note that processors and peripheral interfaces with different operating timings are, for example, a 16-bit peripheral interface for an 8-bit CPU, but a 16-bit peripheral interface is usually accessed by a 16-bit CPU whose processing speed is faster than that of an 8-bit CPU. , normally an 8-bit CPU and a 16-bit peripheral interface are not connected.

[Conventional technology]

FIG. 4 is a time chart illustrating the operation timing of an 8-bit CPU and a 16-bit peripheral interface.

8) As shown in FIG. 4(a), the CPU processes one data in one clock. Also, usually 16-bit C
In the 16-bit peripheral interface accessed by the PU, one data is processed every four clocks, as shown in FIG. 4(b).

As described above, since the operating timings of an 8-bit CPU and a 16-bit peripheral interface are different, conventionally it has not been possible for an 8-bit CPU to access a 16-bit peripheral interface.

Therefore, even if the input/output panels have the same function, different panels are created depending on the CPU to be accessed.

[Problem to be solved by the invention] By the way, an 8-bit CPU and a 16-bit peripheral interface are mounted on one panel, and the 8-bit CPU can handle 16
If it were possible to control the bit peripheral interface, it would be extremely advantageous in terms of storage space and so on.

SUMMARY OF THE INVENTION An object of the present invention is to provide an operation timing control method that enables connection between processors and peripheral interfaces having different operation timings.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, a processor 11 has a control terminal that stops its operation upon input of a predetermined control signal.

The peripheral interface 13 operates with a faster clock than the operating clock of the processor 11, and outputs a data transfer acknowledge signal in response to data acquisition.

In the operation timing control method of the present invention, the processor operation control means 15 is set by the chip select signal sent from the processor 11 when the peripheral interface 13 is accessed, and reset by the data transfer acknowledge signal. Adjust the operation timing by sending a control signal to stop the operation.

[For production]

The processor operation control means 15 according to the present invention stops the operation of the processor 11 and extends data and addresses in response to a chip select signal sent when the processor 11 accesses the peripheral interface 13.

On the other hand, since the peripheral interface 13 operates with a clock different from that of the processor 11, it takes in data and sends out a data transfer acknowledge signal during that time.

The processor operation control means 15 controls the peripheral interface 1
By the data transfer acknowledge signal sent from 3,
By releasing the operational stop state of the processor 11,
Data can be transferred between the processor 11 and the peripheral interface 13, which operate at different timings.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

In the figure, in this embodiment, the processor is an 8-bit C
PU21, 16-hit direct memory access control circuit (16-hit DMAC) 2 as a peripheral interface
2 is shown.

8.Hit CPU 21 and I6B7) DMAC 22 are connected via address bus 23 and data bus 24. The address bus 23 and data bus 24 include
Furthermore, a common RAM 25 and an 8-bit communication interface 26 corresponding to the 8-bit CPU 21 are connected. Note that a disk device and other external storage devices are connected to the 16-bit DMAC 22 to transfer data to and from the RAM 25, and an 8-pinto communication interface 26
A communication line is connected to the terminal to send and receive data.

Further, a decoder 27 is connected to the address bus 23,
The output chip select signal is a 16-bit DMAC
It is input to the C8 terminal of 22. 16 bits) DMAC22
outputs a data transfer acknowledge signal from the DTACK terminal in response to data capture. 8-bit CPU2
1 has an MR terminal that stops its operation upon input of a predetermined control signal.

The feature of the present invention is that in this embodiment, 16-bit I-D MA
It is equipped with a clock 28 that supplies the operating clock CLK of C22, and further includes a clock 28 that supplies the operating clock CLK of R3 as a processor operating side 9111 means.
It is provided with a type flip-flop 29. The set terminal S and input terminal R of the R3 type flip-flop 29 are fixed at high level, the chip select signal output from the decoder 27 is input to the clock terminal CK, and the data output from the 16-bit 1-DMAC 22 is input to the reset terminal R. A transfer acknowledge signal is input, and its purchase output is connected to the MR terminal of the 8-bit cPU 21.

The operation of this embodiment will be described below with reference to the time chart shown in FIG.

The 16-bit DMAC22 (7) operation clock CLK is:
It is set faster than the operating clock of the 8-bit CPU 21.

When the 8-bit CPU 21 accesses the 16-bit DMAc 22, the decoder 27 outputs a chip select signal, sets the R3 type flip-flop 29, and sends a control signal (d output) to the MR terminal of the 8-bit CPU 21. do. The 8-bit CPU 21 holds the address and data in the current state and stops its operation in response to a control signal input to the MR terminal.

The 16-bit DMAC 22 counts a predetermined number of clocks during that time and takes in the data on the data bus 24. Further, the 16-bit DMAC 22 outputs a data transfer acknowledge signal from the DTACK terminal in response to the completion of the data acquisition, and the R3 type flip-flop 29 is reset.
The operation stop state of the 8-bit CPU 21 is released.

〔Effect of the invention〕

As described above, according to the present invention, for example, when the operation timing of a 16-bit peripheral interface is created by an 8-bit processor, the 16-bit peripheral interface can import data by temporarily stopping the operation of the 8-bit processor. I can do it.

In this manner, the operating timings of processors and peripheral interfaces that have different operating timings can be adjusted, allowing them to be accommodated and accessed within one panel.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing the configuration of an embodiment of the invention, Fig. 3 is a time chart explaining the operation of the embodiment of the invention, and Fig. 4 is an 8-bit CPU. 3 is a time chart illustrating the operation timing of a 16-bit peripheral interface. In the figure, 1 is a processor, 3 is a peripheral interface, 5 is a processor operation control means, and 1 is an 8-bit CPU. 2ba] 6-bit DMAC. 3 is an address bus, 4 is a data bus, and 5 is a RAM. 6 is an 8-bit communication interface, 7 is a decoder, 8 is a clock, and 9 is an R3 type flip-flop.

Claims (1)

[Claims] (1) A processor (11) having a control terminal that stops operation upon input of a predetermined control signal;
11) An operation timing control method between the processor (11) and the peripheral interface (13), which operates with a faster clock than the operating clock of the processor (11) and outputs a data transfer acknowledge signal in response to data acquisition. interface(
It is set by the chip select signal sent when accessing the processor (13), and reset by the data transfer acknowledge signal, and during the setting, the processor (11)
1. An operation timing control method characterized by comprising processor operation control means (15) for adjusting the operation timing by sending out a control signal for stopping the operation of the processor.