JPS61116858A - 層間絶縁膜の形成方法 - Google Patents
層間絶縁膜の形成方法Info
- Publication number
- JPS61116858A JPS61116858A JP59223351A JP22335184A JPS61116858A JP S61116858 A JPS61116858 A JP S61116858A JP 59223351 A JP59223351 A JP 59223351A JP 22335184 A JP22335184 A JP 22335184A JP S61116858 A JPS61116858 A JP S61116858A
- Authority
- JP
- Japan
- Prior art keywords
- heat
- insulating film
- heat treatment
- resin
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/48—Insulating materials thereof
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59223351A JPS61116858A (ja) | 1984-10-24 | 1984-10-24 | 層間絶縁膜の形成方法 |
| US06/698,901 US4654113A (en) | 1984-02-10 | 1985-02-06 | Process for fabricating a semiconductor device |
| KR1019850000744A KR900004968B1 (ko) | 1984-02-10 | 1985-02-06 | 반도체장치 제조방법 |
| EP85300829A EP0154419B1 (en) | 1984-02-10 | 1985-02-08 | Process for producing an interconnection structure of a semiconductor device |
| DE8585300829T DE3586109D1 (de) | 1984-02-10 | 1985-02-08 | Verfahren zum herstellen einer verbindungsstruktur von einer halbleiteranordnung. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59223351A JPS61116858A (ja) | 1984-10-24 | 1984-10-24 | 層間絶縁膜の形成方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61116858A true JPS61116858A (ja) | 1986-06-04 |
| JPH0329298B2 JPH0329298B2 (https=) | 1991-04-23 |
Family
ID=16796799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59223351A Granted JPS61116858A (ja) | 1984-02-10 | 1984-10-24 | 層間絶縁膜の形成方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61116858A (https=) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61144849A (ja) * | 1984-12-19 | 1986-07-02 | Seiko Epson Corp | 半導体装置の製造方法 |
| JPS61196555A (ja) * | 1985-02-26 | 1986-08-30 | Nec Corp | 多層配線の形成方法 |
| JPS62176147A (ja) * | 1985-10-03 | 1987-08-01 | ビュル エス.アー. | 高密度集積回路の構成要素の相互接続用多層金属配線網の形成法及び本形成法によつて形成される集積回路 |
| JPS62295437A (ja) * | 1986-06-14 | 1987-12-22 | Yamaha Corp | 多層配線形成法 |
| JPH03201438A (ja) * | 1989-12-28 | 1991-09-03 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
| KR970023723A (ko) * | 1995-10-20 | 1997-05-30 | 김주용 | 반도체 소자의 금속 배선 방법 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5768050A (en) * | 1980-10-15 | 1982-04-26 | Hitachi Ltd | Multilayer wire structure and manufacture thereof |
-
1984
- 1984-10-24 JP JP59223351A patent/JPS61116858A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5768050A (en) * | 1980-10-15 | 1982-04-26 | Hitachi Ltd | Multilayer wire structure and manufacture thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61144849A (ja) * | 1984-12-19 | 1986-07-02 | Seiko Epson Corp | 半導体装置の製造方法 |
| JPS61196555A (ja) * | 1985-02-26 | 1986-08-30 | Nec Corp | 多層配線の形成方法 |
| JPS62176147A (ja) * | 1985-10-03 | 1987-08-01 | ビュル エス.アー. | 高密度集積回路の構成要素の相互接続用多層金属配線網の形成法及び本形成法によつて形成される集積回路 |
| JPS62295437A (ja) * | 1986-06-14 | 1987-12-22 | Yamaha Corp | 多層配線形成法 |
| JPH03201438A (ja) * | 1989-12-28 | 1991-09-03 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
| KR970023723A (ko) * | 1995-10-20 | 1997-05-30 | 김주용 | 반도체 소자의 금속 배선 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0329298B2 (https=) | 1991-04-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0137927B1 (en) | Process for the controlled etching of tapered vias in borosilicate glass dielectrics | |
| JPS6254454A (ja) | 集積回路上の絶縁性構成体及びその製造方法 | |
| DE69627233T2 (de) | Verfahren zum Herstellen einer Halbleiteranordnung mit einer Mehrschichtverbindungsstruktur, mit einem verbesserten Schritt zum Herstellen einer dielektrischen Zwischenschicht | |
| JPS5818938A (ja) | 集積回路構造体 | |
| US5517062A (en) | Stress released VLSI structure by the formation of porous intermetal layer | |
| KR970007114B1 (ko) | 반도체 소자 제조 방법 | |
| JPS61116858A (ja) | 層間絶縁膜の形成方法 | |
| JPH01225326A (ja) | 集積回路のパッシベーション方法 | |
| JP3077990B2 (ja) | 半導体装置の製造方法 | |
| US4988405A (en) | Fabrication of devices utilizing a wet etchback procedure | |
| JP2738033B2 (ja) | 多層配線構造体の製造方法 | |
| JPS61154148A (ja) | 半導体装置の製造方法 | |
| JPS63302537A (ja) | 集積回路の製造方法 | |
| JPH04370934A (ja) | 半導体装置の製造方法 | |
| JPH0265256A (ja) | 半導体装置の製造方法 | |
| JPH11251312A (ja) | 半導体装置の製造方法 | |
| JPH0430524A (ja) | 半導体装置の製造方法 | |
| JP2001189310A (ja) | 半導体装置の製造方法 | |
| JPS5946419B2 (ja) | 半導体装置におけるポリイミド膜の形成方法 | |
| JPS63164342A (ja) | 絶縁膜形成方法 | |
| JPS5969950A (ja) | 多層配線形成方法 | |
| JPH0427703B2 (https=) | ||
| JPS61232636A (ja) | 半導体装置の製造方法 | |
| JPS59225526A (ja) | 平坦化方法 | |
| JPS60148125A (ja) | プラズマcvd法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |