JPS6079451A - 入出力装置ゼネレ−シヨン方式 - Google Patents

入出力装置ゼネレ−シヨン方式

Info

Publication number
JPS6079451A
JPS6079451A JP58188148A JP18814883A JPS6079451A JP S6079451 A JPS6079451 A JP S6079451A JP 58188148 A JP58188148 A JP 58188148A JP 18814883 A JP18814883 A JP 18814883A JP S6079451 A JPS6079451 A JP S6079451A
Authority
JP
Japan
Prior art keywords
input
output device
load module
volume
card deck
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58188148A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0115101B2 (cg-RX-API-DMAC7.html
Inventor
Shinya Tanno
丹野　信哉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58188148A priority Critical patent/JPS6079451A/ja
Publication of JPS6079451A publication Critical patent/JPS6079451A/ja
Publication of JPH0115101B2 publication Critical patent/JPH0115101B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP58188148A 1983-10-07 1983-10-07 入出力装置ゼネレ−シヨン方式 Granted JPS6079451A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58188148A JPS6079451A (ja) 1983-10-07 1983-10-07 入出力装置ゼネレ−シヨン方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58188148A JPS6079451A (ja) 1983-10-07 1983-10-07 入出力装置ゼネレ−シヨン方式

Publications (2)

Publication Number Publication Date
JPS6079451A true JPS6079451A (ja) 1985-05-07
JPH0115101B2 JPH0115101B2 (cg-RX-API-DMAC7.html) 1989-03-15

Family

ID=16218585

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58188148A Granted JPS6079451A (ja) 1983-10-07 1983-10-07 入出力装置ゼネレ−シヨン方式

Country Status (1)

Country Link
JP (1) JPS6079451A (cg-RX-API-DMAC7.html)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5572230A (en) * 1978-11-24 1980-05-30 Toshiba Corp Automatic editing unit for input-output control program
JPS55162130A (en) * 1979-06-05 1980-12-17 Nec Corp Program control system of terminal equipment
JPS57150019A (en) * 1981-03-13 1982-09-16 Hitachi Ltd Control system of terminal device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5572230A (en) * 1978-11-24 1980-05-30 Toshiba Corp Automatic editing unit for input-output control program
JPS55162130A (en) * 1979-06-05 1980-12-17 Nec Corp Program control system of terminal equipment
JPS57150019A (en) * 1981-03-13 1982-09-16 Hitachi Ltd Control system of terminal device

Also Published As

Publication number Publication date
JPH0115101B2 (cg-RX-API-DMAC7.html) 1989-03-15

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