JPS6059756A - プラグインパッケ−ジとその製造方法 - Google Patents
プラグインパッケ−ジとその製造方法Info
- Publication number
- JPS6059756A JPS6059756A JP58168025A JP16802583A JPS6059756A JP S6059756 A JPS6059756 A JP S6059756A JP 58168025 A JP58168025 A JP 58168025A JP 16802583 A JP16802583 A JP 16802583A JP S6059756 A JPS6059756 A JP S6059756A
- Authority
- JP
- Japan
- Prior art keywords
- plug
- board
- substrate
- package
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58168025A JPS6059756A (ja) | 1983-09-12 | 1983-09-12 | プラグインパッケ−ジとその製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58168025A JPS6059756A (ja) | 1983-09-12 | 1983-09-12 | プラグインパッケ−ジとその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6059756A true JPS6059756A (ja) | 1985-04-06 |
| JPH0558262B2 JPH0558262B2 (enExample) | 1993-08-26 |
Family
ID=15860416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58168025A Granted JPS6059756A (ja) | 1983-09-12 | 1983-09-12 | プラグインパッケ−ジとその製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6059756A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06112271A (ja) * | 1992-08-12 | 1994-04-22 | Internatl Business Mach Corp <Ibm> | ダイレクト・チップ・アタッチ・モジュール |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4923624A (enExample) * | 1972-06-22 | 1974-03-02 | ||
| JPS4957372A (enExample) * | 1972-10-04 | 1974-06-04 | ||
| JPS5489273U (enExample) * | 1977-12-08 | 1979-06-23 | ||
| JPS5517472U (enExample) * | 1978-07-20 | 1980-02-04 | ||
| JPS55103751A (en) * | 1979-01-31 | 1980-08-08 | Nec Corp | Semiconductor device |
| JPS5631872U (enExample) * | 1979-08-17 | 1981-03-28 | ||
| JPS56103491A (en) * | 1980-01-23 | 1981-08-18 | Hitachi Ltd | Semiconductor device |
| JPS5784750U (enExample) * | 1980-11-14 | 1982-05-25 | ||
| JPS5810848A (ja) * | 1981-07-14 | 1983-01-21 | Toshiba Corp | 混成集積回路用リ−ドピン |
| JPS5810840A (ja) * | 1981-07-10 | 1983-01-21 | Fujitsu Ltd | 半導体装置 |
| JPS58159355A (ja) * | 1982-03-17 | 1983-09-21 | Nec Corp | 半導体装置の製造方法 |
-
1983
- 1983-09-12 JP JP58168025A patent/JPS6059756A/ja active Granted
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4923624A (enExample) * | 1972-06-22 | 1974-03-02 | ||
| JPS4957372A (enExample) * | 1972-10-04 | 1974-06-04 | ||
| JPS5489273U (enExample) * | 1977-12-08 | 1979-06-23 | ||
| JPS5517472U (enExample) * | 1978-07-20 | 1980-02-04 | ||
| JPS55103751A (en) * | 1979-01-31 | 1980-08-08 | Nec Corp | Semiconductor device |
| JPS5631872U (enExample) * | 1979-08-17 | 1981-03-28 | ||
| JPS56103491A (en) * | 1980-01-23 | 1981-08-18 | Hitachi Ltd | Semiconductor device |
| JPS5784750U (enExample) * | 1980-11-14 | 1982-05-25 | ||
| JPS5810840A (ja) * | 1981-07-10 | 1983-01-21 | Fujitsu Ltd | 半導体装置 |
| JPS5810848A (ja) * | 1981-07-14 | 1983-01-21 | Toshiba Corp | 混成集積回路用リ−ドピン |
| JPS58159355A (ja) * | 1982-03-17 | 1983-09-21 | Nec Corp | 半導体装置の製造方法 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06112271A (ja) * | 1992-08-12 | 1994-04-22 | Internatl Business Mach Corp <Ibm> | ダイレクト・チップ・アタッチ・モジュール |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0558262B2 (enExample) | 1993-08-26 |
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