JPS602832U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS602832U
JPS602832U JP1983094705U JP9470583U JPS602832U JP S602832 U JPS602832 U JP S602832U JP 1983094705 U JP1983094705 U JP 1983094705U JP 9470583 U JP9470583 U JP 9470583U JP S602832 U JPS602832 U JP S602832U
Authority
JP
Japan
Prior art keywords
emitter
electrode
semiconductor equipment
sides
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983094705U
Other languages
English (en)
Inventor
伸一 伊藤
寺嶋 二郎
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP1983094705U priority Critical patent/JPS602832U/ja
Publication of JPS602832U publication Critical patent/JPS602832U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第1図は従来のパワートランジスタの平面図、第2図は
本考案の一実施例のパワートランジスタの平面図である
。 1・・・シリコンチップ、2・・・ベース電極、31゜
32・・・エミッタ電極、71.72・・・エミッタリ
ード線、8・・・エミッタ端子。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素体の表面の中央部にベース電極、その両側にエ
    ミッタ電極を有するものにおいて、半導体素体のエミッ
    タ電極が位置する側と同じ両側に互に連結されたエミッ
    タ端子が設けられ、該各エミッタ端子がそれぞれ近くに
    位置するニーミッタ電極とほぼ等しい長さのエミッタリ
    ード線によって接続されたことを特徴とする半導体装置
JP1983094705U 1983-06-20 1983-06-20 半導体装置 Pending JPS602832U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983094705U JPS602832U (ja) 1983-06-20 1983-06-20 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983094705U JPS602832U (ja) 1983-06-20 1983-06-20 半導体装置

Publications (1)

Publication Number Publication Date
JPS602832U true JPS602832U (ja) 1985-01-10

Family

ID=30226555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983094705U Pending JPS602832U (ja) 1983-06-20 1983-06-20 半導体装置

Country Status (1)

Country Link
JP (1) JPS602832U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01296632A (ja) * 1988-05-25 1989-11-30 Mitsubishi Electric Corp 半導体装置
JP2006210786A (ja) * 2005-01-31 2006-08-10 Matsushita Electric Ind Co Ltd トランジスタ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01296632A (ja) * 1988-05-25 1989-11-30 Mitsubishi Electric Corp 半導体装置
JP2006210786A (ja) * 2005-01-31 2006-08-10 Matsushita Electric Ind Co Ltd トランジスタ

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