JPS59152750U - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS59152750U JPS59152750U JP1983047403U JP4740383U JPS59152750U JP S59152750 U JPS59152750 U JP S59152750U JP 1983047403 U JP1983047403 U JP 1983047403U JP 4740383 U JP4740383 U JP 4740383U JP S59152750 U JPS59152750 U JP S59152750U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- electrode
- diode
- conductive
- conductive wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図はトーテムポール回路の回路図、第2図は本考案
の一実施例の封止前の状態を示す平面図、第3図ないし
第5図はそれぞれ異なる実施例の同様の状態を示す平面
図である。 1.3:トランジスタ、2.4:ダイオード、21.2
2:’J−ドフレームマウント部、23゜24.25,
26:リードフレームリード部、31、 32. 33
. 34. 35. 36:端子。
の一実施例の封止前の状態を示す平面図、第3図ないし
第5図はそれぞれ異なる実施例の同様の状態を示す平面
図である。 1.3:トランジスタ、2.4:ダイオード、21.2
2:’J−ドフレームマウント部、23゜24.25,
26:リードフレームリード部、31、 32. 33
. 34. 35. 36:端子。
Claims (1)
- 1枚の絶縁基板の上面にそれぞれダイオードの一方の電
極面およびトランジスタのコレクタ電極面が被着した2
枚の導体板、それぞれ前記ダイオードの他方の電極およ
び前記トランジスタのエミッタ電極と導線によって接続
された2枚の導体板ならひにトランジスタのベース電極
と導線によって接続された2枚の導体板が被着し、前記
ダイオードおよびトランジスタならびに導線を覆い、前
記絶縁基板の下面ならびに各導体板から同一平面に引き
出された端子を露出させた絶縁物により封止されたこと
を特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983047403U JPS59152750U (ja) | 1983-03-31 | 1983-03-31 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983047403U JPS59152750U (ja) | 1983-03-31 | 1983-03-31 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59152750U true JPS59152750U (ja) | 1984-10-13 |
Family
ID=30177951
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1983047403U Pending JPS59152750U (ja) | 1983-03-31 | 1983-03-31 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59152750U (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02130953A (ja) * | 1988-11-11 | 1990-05-18 | Fuji Electric Co Ltd | トランジスタモジュール |
JPH02130954A (ja) * | 1988-11-11 | 1990-05-18 | Fuji Electric Co Ltd | 逆阻止形トランジスタモジュール |
-
1983
- 1983-03-31 JP JP1983047403U patent/JPS59152750U/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02130953A (ja) * | 1988-11-11 | 1990-05-18 | Fuji Electric Co Ltd | トランジスタモジュール |
JPH02130954A (ja) * | 1988-11-11 | 1990-05-18 | Fuji Electric Co Ltd | 逆阻止形トランジスタモジュール |
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