JPS60140737A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS60140737A
JPS60140737A JP58251594A JP25159483A JPS60140737A JP S60140737 A JPS60140737 A JP S60140737A JP 58251594 A JP58251594 A JP 58251594A JP 25159483 A JP25159483 A JP 25159483A JP S60140737 A JPS60140737 A JP S60140737A
Authority
JP
Japan
Prior art keywords
bump
film
pad
conductive film
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58251594A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0244145B2 (en, 2012
Inventor
Toshiaki Kumada
熊田　敏明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP58251594A priority Critical patent/JPS60140737A/ja
Publication of JPS60140737A publication Critical patent/JPS60140737A/ja
Publication of JPH0244145B2 publication Critical patent/JPH0244145B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP58251594A 1983-12-27 1983-12-27 半導体装置の製造方法 Granted JPS60140737A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58251594A JPS60140737A (ja) 1983-12-27 1983-12-27 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58251594A JPS60140737A (ja) 1983-12-27 1983-12-27 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS60140737A true JPS60140737A (ja) 1985-07-25
JPH0244145B2 JPH0244145B2 (en, 2012) 1990-10-02

Family

ID=17225136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58251594A Granted JPS60140737A (ja) 1983-12-27 1983-12-27 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS60140737A (en, 2012)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5057453A (en) * 1987-10-21 1991-10-15 Kabushiki Kaisha Toshiba Method for making a semiconductor bump electrode with a skirt
US5242861A (en) * 1991-06-06 1993-09-07 Nec Corporation Method for manufacturing semiconductor device having a multilayer wiring structure
US5492235A (en) * 1995-12-18 1996-02-20 Intel Corporation Process for single mask C4 solder bump fabrication

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53131766A (en) * 1977-04-22 1978-11-16 Hitachi Ltd Semiconductor device electrode structural body and production of the same
JPS57198647A (en) * 1981-06-01 1982-12-06 Nec Corp Semiconductor device and manufacture therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53131766A (en) * 1977-04-22 1978-11-16 Hitachi Ltd Semiconductor device electrode structural body and production of the same
JPS57198647A (en) * 1981-06-01 1982-12-06 Nec Corp Semiconductor device and manufacture therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5057453A (en) * 1987-10-21 1991-10-15 Kabushiki Kaisha Toshiba Method for making a semiconductor bump electrode with a skirt
US5242861A (en) * 1991-06-06 1993-09-07 Nec Corporation Method for manufacturing semiconductor device having a multilayer wiring structure
US5492235A (en) * 1995-12-18 1996-02-20 Intel Corporation Process for single mask C4 solder bump fabrication

Also Published As

Publication number Publication date
JPH0244145B2 (en, 2012) 1990-10-02

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term