JPS5975723A - プログラマブルカウンタ - Google Patents
プログラマブルカウンタInfo
- Publication number
- JPS5975723A JPS5975723A JP57187101A JP18710182A JPS5975723A JP S5975723 A JPS5975723 A JP S5975723A JP 57187101 A JP57187101 A JP 57187101A JP 18710182 A JP18710182 A JP 18710182A JP S5975723 A JPS5975723 A JP S5975723A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- level
- clock signal
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/58—Gating or clocking signals not applied to all stages, i.e. asynchronous counters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/16—Circuits for carrying over pulses between successive decades
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/58—Gating or clocking signals not applied to all stages, i.e. asynchronous counters
- H03K23/62—Gating or clocking signals not applied to all stages, i.e. asynchronous counters reversible
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57187101A JPS5975723A (ja) | 1982-10-25 | 1982-10-25 | プログラマブルカウンタ |
| US06/542,195 US4587665A (en) | 1982-10-15 | 1983-10-14 | Binary counter having buffer and coincidence circuits for the switched bistable stages thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57187101A JPS5975723A (ja) | 1982-10-25 | 1982-10-25 | プログラマブルカウンタ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5975723A true JPS5975723A (ja) | 1984-04-28 |
| JPH0156572B2 JPH0156572B2 (enrdf_load_stackoverflow) | 1989-11-30 |
Family
ID=16200118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57187101A Granted JPS5975723A (ja) | 1982-10-15 | 1982-10-25 | プログラマブルカウンタ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5975723A (enrdf_load_stackoverflow) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01256223A (ja) * | 1988-03-07 | 1989-10-12 | Digital Equip Corp <Dec> | ロード可能なリプルカウンタ |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS553252A (en) * | 1978-06-21 | 1980-01-11 | Mitsubishi Electric Corp | Preset circuit |
| JPS56747A (en) * | 1979-06-18 | 1981-01-07 | Toshiba Corp | Binary counter circuit |
-
1982
- 1982-10-25 JP JP57187101A patent/JPS5975723A/ja active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS553252A (en) * | 1978-06-21 | 1980-01-11 | Mitsubishi Electric Corp | Preset circuit |
| JPS56747A (en) * | 1979-06-18 | 1981-01-07 | Toshiba Corp | Binary counter circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01256223A (ja) * | 1988-03-07 | 1989-10-12 | Digital Equip Corp <Dec> | ロード可能なリプルカウンタ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0156572B2 (enrdf_load_stackoverflow) | 1989-11-30 |
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