JPS59128736U - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPS59128736U
JPS59128736U JP1984004773U JP477384U JPS59128736U JP S59128736 U JPS59128736 U JP S59128736U JP 1984004773 U JP1984004773 U JP 1984004773U JP 477384 U JP477384 U JP 477384U JP S59128736 U JPS59128736 U JP S59128736U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
semiconductor integrated
bonding pads
external lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1984004773U
Other languages
English (en)
Other versions
JPS6214689Y2 (ja
Inventor
喜岡 隆一
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1984004773U priority Critical patent/JPS59128736U/ja
Publication of JPS59128736U publication Critical patent/JPS59128736U/ja
Application granted granted Critical
Publication of JPS6214689Y2 publication Critical patent/JPS6214689Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第1図a、  bは従来の音響用電力増幅半導体集積回
路装置の一例の外形図、第2図は第1図a。 bの音響用電力増幅半導体集積回路装置の実装例を示す
説明図、第3図a、  bはそれぞれ第1図a。 bに示す音響用電力増幅半導体集積回路装置の内  一
部を説明する説明図、第4図a、  bは本考案の一実
施例を示す音響用電力増幅半導体集積回路装置の外形図
、第5図a、  bはそれぞれ第4図a、  bに示さ
れる音響用電力増幅半導体集積回路装置の内部を説明す
る説明図である。 11、 12. 19. 20・・・音響用電力増幅半
導体集積回路装置、13・・・放熱板、14.14’。 40.50・・・半導体ペレット、15.15’。 45.55・・・放熱板、16−1・・・16−7.1
6−1′・・・16−7’ 、46−1・・・46−7
.56−1・・・56−7・・・リード、17. 17
’、47゜57.47’ 、57’・・・ボンディング
線、18−1・・・1B−7,18−1’・・・1B−
7’、21〜27.31〜37・・・ポンディングパッ
ド。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体ペレット上の多数のポンディングパッドが第1の
    電流容量をもつ導電路で外部導出用リードに接続される
    複数の第1のポンディングパッドと前記第1の電流容量
    とは異なる第2の電流容量をもつ導電路で外部導出用リ
    ードに接続される複数の第2のポンディングパッドとで
    構成されている半導体集積回路装置において、前記複数
    の第2のポンディングパッドは前記半導体ペレットの中
    心線に対して対称に配置されていることを特徴とする半
    導体集積回路装置。
JP1984004773U 1984-01-17 1984-01-17 半導体集積回路装置 Granted JPS59128736U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984004773U JPS59128736U (ja) 1984-01-17 1984-01-17 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984004773U JPS59128736U (ja) 1984-01-17 1984-01-17 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS59128736U true JPS59128736U (ja) 1984-08-30
JPS6214689Y2 JPS6214689Y2 (ja) 1987-04-15

Family

ID=30136373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984004773U Granted JPS59128736U (ja) 1984-01-17 1984-01-17 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS59128736U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986005322A1 (en) * 1985-02-28 1986-09-12 Sony Corporation Semiconducteur circuit device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131381U (ja) * 1973-03-14 1974-11-12
JPS49131381A (ja) * 1973-04-18 1974-12-17
JPS523384A (en) * 1975-06-24 1977-01-11 Siemens Ag Comb teeth shaped conductor for semiconductor elements or integrated circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131381U (ja) * 1973-03-14 1974-11-12
JPS49131381A (ja) * 1973-04-18 1974-12-17
JPS523384A (en) * 1975-06-24 1977-01-11 Siemens Ag Comb teeth shaped conductor for semiconductor elements or integrated circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986005322A1 (en) * 1985-02-28 1986-09-12 Sony Corporation Semiconducteur circuit device

Also Published As

Publication number Publication date
JPS6214689Y2 (ja) 1987-04-15

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