JPS5891621A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPS5891621A
JPS5891621A JP56190228A JP19022881A JPS5891621A JP S5891621 A JPS5891621 A JP S5891621A JP 56190228 A JP56190228 A JP 56190228A JP 19022881 A JP19022881 A JP 19022881A JP S5891621 A JPS5891621 A JP S5891621A
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JP
Japan
Prior art keywords
semiconductor layer
pattern
deposited
film
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56190228A
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English (en)
Inventor
Tadashi Nishimura
正 西村
Yoji Masuko
益子 洋治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56190228A priority Critical patent/JPS5891621A/ja
Priority to US06/444,095 priority patent/US4414242A/en
Priority to FR8219783A priority patent/FR2517123A1/fr
Publication of JPS5891621A publication Critical patent/JPS5891621A/ja
Pending legal-status Critical Current

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    • H01L21/02521Materials
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 この発明は半導体装置の製造方法、特に絶縁体上に半導
体単結晶膜を形成する方法に関するものである。
半導体装置の烏速化、高vR度化の丸め、Lgl路襦子
をlI鴫体で分離して浮遊容量の少ない半導体集積回路
を製造する試みがなされており、その一方法として絶縁
体上に島状の半導体結晶を形成し、その半導体結晶中に
回路系子を構成する方法がある。この半導体単結晶を形
成する方法として、絶縁体上に多結晶または非晶質の半
導体膜を堆積し、その表面にレーザ光もしくは“鑵子繊
等のエネルギー線を照射することにより表面層のみを加
熱し、単結晶の半導体膜を形成する方法がある。
このような従来の方法の一例を作製方法を図に示しなが
ら説明する。第1図(a)において、叫は基板となるべ
、き石英基板(Slow )、(川はその上に通常の減
圧CVD法によってたい積させられた厚さ一500OA
のポリシリコンをホす。これを−1図(切に示すように
950℃の酸化ふんい気で成長させた600Aの酸化1
1He、減圧CVD法によってたーい積させられた1O
OOAo′1ill化膜霞によっておおい、写真製版工
程を経て、第1図(C)のごとく窒化fIIll:ll
をパターニングする。これを950℃の酸化ふん囲気に
長時間ざらし、盪化膜(Ilのパターンのない部分をす
べて酸化してしまつ友後、窒化(−とその下敷の酸化m
μ匂を除去すれば、51i1図(d)に示すごとくポリ
シリコンが周囲と下部を絶縁物である二酸化シリコンす
なわち石英ガラスで囲まれた形状を得ることができる。
しかし、このままではポリシリコンがデバイス形成可能
な結晶性をもたないため、細くしぼったレーザ光あるい
は電子ビーム等のエネルギー線で、このポリシリコンを
溶融させ単結晶化ないしは大きな粒径のポリシリコンに
する必要があもところが従来の方法ではエネルギー線を
照射してもポリシリコンを囲む絶縁層において下部方向
と周囲方向の熱放散が制御されないため、往々にして周
辺から早く循却され結晶核が多く生じ、単結晶化はおろ
か大きな粒径を得ることも比較的固−(、、、ありえ。
。t’i、e asオ、ヵよよ、工、2−、ヵを使用す
る場合には、絶縁物、例えば100OA 11 jiE
の窒化膜illを′Is1図+e)に示すようにたい積
させることにより熱伝導状態を劃−して単結晶を得るこ
とができる。しかし、この方法ではす゛べてのエネルギ
ー線への使用は困#ACあり、またレーザ光を使用する
場合にもこの窒化膜0りが反射防止膜となるためにこの
膜の厚みの微小な変化が照射されるパワーの変動となり
再現性の上で1!l趙ρfある。第2図はこの再結晶化
された島状のシリコン層を出発材料としてMO8−)ラ
ンジスタを形成する46合の形成方法の一例を示してい
る。7リコンゲートのM08トランジスタ形成プロセス
は公知であるので詳しくは述べないが、先ず問題は第2
図(b)に示すゲート威化膜(2)において生じる。す
なわち、再結晶化された島状シリコン層の粒径、結晶軸
り制御がされていないため、形#fcされた酸化A厚に
ノくラツキが生じる。また界面罐荷も一様Cはない。
このため、得られたMO8トランジスタ特性がウェハ内
あるいはウエノ’ff1l′r!バラツクことになる。
ちなみに、42図(C)は写真製版されたポリシリコン
ゲート四、第2図(d)はソースドレイン−が形成され
ているところを示し、$2図(8)で層間絶縁1!11
G!4゜アルミニウムによる配線に)9表Eii保−膜
四が形成されデバイスが完成されることを示している。
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、半導体層を形成するlこあたって
、それに先がけ下地の絶縁ノー上に少なくとも1個所以
上の凸部を形成しておき、エネルギー線による半導体、
拝一時に熱伝導状順を制御し、再結晶化した半導体層の
膜質の向上と均′貢比を9詣とすることを目的としてい
る。
以下、この発明の一実施例を図により説明する。
83図(a)は石英基板cl(lを示す。これに第3図
(1))のようにレジストでライン幅2μm、ライン間
隔dμmのパターン形成を行う。これをしかるべきエツ
チングガス中での反応性イオンエツチングを行い、石英
基板に深さ3C100Aのダレイテイグパクー/トシて
形成し、レジストを除去したものlバ第3図(C)であ
る。この後は第1図で述べた方法と同様に第3図(d)
に示rように減圧OVD法でポリシリコン層(11)を
500OAたい積し、第3図(e)に示すように950
℃で酸化して酸化1lI(12)を形成し、減圧OVD
法による窒化@O′4をたい積し、写真製版によるこの
窒化膜0:4のパターニングを行う、これを第3図(f
)に承すように950’C1l化ふんい気に長時間さら
した後、バクー二ングされた窒化膜霞および酸化sag
を除去する。183図(g) (h)は第3図(θ)の
平面図を示す。
@3図伝)に示す島状ポリシリコン層111)のパター
ンの大きさは短辺40μm、長辺80μmで、条溝を4
本ふくんでいる。#!3図但)に示すパターンは短辺1
0μm、長辺80μmで条溝が1本だけパターン中心部
に設けられている。条溝の幅1間隔はエネルギー線のス
ポットサイズ、すなわち照射時にf1111!lする面
積によって決められるもので、この例では直径50〜6
0μmlのレーザ光を用いるので、条溝の幅と間隔はそ
の和がレーザ光の直径の115程度となるよう、幅2μ
m9間隔8μmを用いる。第3図(f)の構造をレーザ
光を走査しながら照射する。この時走査方間は条溝と並
行でも直角でもよいが、パターンの大きさが、スポット
径を越える場合は長手方向に走査するのがよい。このよ
うにレーザ光を照射すると、ポリシリコン層(II)は
溶融するが、固化にあたっては、条溝の凸の部分の上部
のシリコンが他に比べてうすいため早(冷えるので、結
1化の核になる。また、この条溝の壁面が結晶軸を現定
し、小さなパタ−ンでは全面単結晶に、大きなパターン
でも非常に大きな結晶粒をもった再結晶層となる。この
後のデバイス形成方法については従来方法と同じである
なお、上記実施例では、レーザをエネルギー線として用
い゛たが、電子ビーム゛の場合も同様の効果が得られる
ことはいうまでもない。
また、条溝の形成にあたっては、全面に形成したが、マ
スク合せによって部分的にパターン部のみメζ形成して
もよく、その断面形状が矩形である必要はない。適当な
傾きをも之せることにより、面方位の制(至)が−T能
である。
以上のようにこの発明によれば、半辱体mを絶(織物で
周囲と下部を囲むに峰して、熱伝導制御のための514
褥を下部絶縁体表面に形成しているのでエネにギー線に
よる溶融後の再結晶化iこおいて単結晶または非常に大
きな結晶粒をもつ次半導体層が再現性よく形成され、こ
れにより形成されるデバイスの特性が向上かつ安定化す
るという効果がある。
【図面の簡単な説明】
第1rgは従来の島状半導体層を形成する方法を示す工
程別断面図、#!2図は従来の島状半導体層を用いてM
OS −トランジスタを形成する方法を示す工程別断面
図、ag3図はこの発明の一実施例による島状半導体層
を形成する方法を示す工程別断面図である。 閣は石英基板、(!りはポリシリコン層、tIzは酸化
膜、 (11は電化膜、(14は(+1)のポリシリコ
ンがすべて酸化されて形成された酸化膜、Ooは電化膜
、3υはゲート酸化膜、qはゲートポリシリコン電極、
瞬は砒素をドーピングして形成したソースドレイン領域
、鱒は層間絶縁膜、に)は配線用At層、…は    
□表面保1k[、■はレジストによるダレイティングパ
ターン。 なお、図中同一符号は同−又は相当部分を示九第1図 Ca) 第2r21 (jり

Claims (3)

    【特許請求の範囲】
  1. (1)絶縁体上に形成され周囲を絶縁体によって取り囲
    まれた島状の多結晶または非晶質の半導体層を局部加熱
    により、局部的にm−する方法において、上記島状の半
    導体層の下地となる絶縁体上に少なくとも1個所以上の
    凸部を半導体層形成に先がけて、あらかじめ形成してお
    (ことを特徴とする半導体装置の製造方法。
  2. (2)  局部加熱はレーザ光または電子ビームによっ
    て行なわれることを特徴とする特1FFal!求の範囲
    第1項記載の半導体装置の製造方法。
  3. (3)  局部加熱はレーザ光または電子ビームを半導
    体層に対して相対的に移動することにより行なわれるこ
    とを特徴とする特#F#ll求の範囲第1項または第2
    項のいずれかに記載の半導体装置の製造方法。
JP56190228A 1981-11-26 1981-11-26 半導体装置の製造方法 Pending JPS5891621A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP56190228A JPS5891621A (ja) 1981-11-26 1981-11-26 半導体装置の製造方法
US06/444,095 US4414242A (en) 1981-11-26 1982-11-24 Process for fabricating a semiconductor device
FR8219783A FR2517123A1 (fr) 1981-11-26 1982-11-25 Procede de formation d'une pellicule semi-conductrice monocristalline sur un isolant

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56190228A JPS5891621A (ja) 1981-11-26 1981-11-26 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPS5891621A true JPS5891621A (ja) 1983-05-31

Family

ID=16254612

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (3)

Country Link
US (1) US4414242A (ja)
JP (1) JPS5891621A (ja)
FR (1) FR2517123A1 (ja)

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US4556524A (en) * 1981-11-10 1985-12-03 The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland Method for preparing digital storage device by laser application
JPS58115832A (ja) * 1981-12-28 1983-07-09 Fujitsu Ltd 半導体装置の製造方法
JPS59108313A (ja) * 1982-12-13 1984-06-22 Mitsubishi Electric Corp 半導体単結晶層の製造方法
JPS59205712A (ja) * 1983-04-30 1984-11-21 Fujitsu Ltd 半導体装置の製造方法
US4619034A (en) * 1983-05-02 1986-10-28 Ncr Corporation Method of making laser recrystallized silicon-on-insulator nonvolatile memory device
US4559102A (en) * 1983-05-09 1985-12-17 Sony Corporation Method for recrystallizing a polycrystalline, amorphous or small grain material
JPS6089953A (ja) * 1983-10-22 1985-05-20 Agency Of Ind Science & Technol 積層型半導体装置の製造方法
KR900001267B1 (ko) * 1983-11-30 1990-03-05 후지쓰 가부시끼가이샤 Soi형 반도체 장치의 제조방법
US4564403A (en) * 1984-01-27 1986-01-14 Sony Corporation Research Center Single-crystal semiconductor devices and method for making them
US4496608A (en) * 1984-03-02 1985-01-29 Xerox Corporation P-Glass reflow technique
US4719183A (en) * 1984-10-03 1988-01-12 Sharp Kabushiki Kaisha Forming single crystal silicon on insulator by irradiating a laser beam having dual peak energy distribution onto polysilicon on a dielectric substrate having steps
US5456763A (en) * 1994-03-29 1995-10-10 The Regents Of The University Of California Solar cells utilizing pulsed-energy crystallized microcrystalline/polycrystalline silicon
EP0973203A3 (de) * 1998-07-17 2001-02-14 Infineon Technologies AG Halbleiterschicht mit lateral veränderlicher Dotierung und Verfahren zu dessen Herstellung
US7553740B2 (en) * 2005-05-26 2009-06-30 Fairchild Semiconductor Corporation Structure and method for forming a minimum pitch trench-gate FET with heavy body region

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55115341A (en) * 1979-02-28 1980-09-05 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
US4269631A (en) * 1980-01-14 1981-05-26 International Business Machines Corporation Selective epitaxy method using laser annealing for making filamentary transistors
US4303455A (en) * 1980-03-14 1981-12-01 Rockwell International Corporation Low temperature microwave annealing of semiconductor devices
JPS56135969A (en) * 1980-03-27 1981-10-23 Fujitsu Ltd Manufacture of semiconductor device
US4372990A (en) * 1980-06-23 1983-02-08 Texas Instruments Incorporated Retaining wall technique to maintain physical shape of material during transient radiation annealing
JPS5791518A (en) * 1980-11-28 1982-06-07 Toshiba Corp Manufacture of semiconductor device
JPS57145316A (en) * 1981-03-04 1982-09-08 Toshiba Corp Manufacture of semicondcutor device

Also Published As

Publication number Publication date
FR2517123B1 (ja) 1985-01-11
FR2517123A1 (fr) 1983-05-27
US4414242A (en) 1983-11-08

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