JPS58216437A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS58216437A
JPS58216437A JP10110182A JP10110182A JPS58216437A JP S58216437 A JPS58216437 A JP S58216437A JP 10110182 A JP10110182 A JP 10110182A JP 10110182 A JP10110182 A JP 10110182A JP S58216437 A JPS58216437 A JP S58216437A
Authority
JP
Japan
Prior art keywords
silicon substrate
nitride film
groove
impurity
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10110182A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6312380B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Makoto Hirayama
誠 平山
Natsuo Tsubouchi
坪内　夏朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10110182A priority Critical patent/JPS58216437A/ja
Publication of JPS58216437A publication Critical patent/JPS58216437A/ja
Publication of JPS6312380B2 publication Critical patent/JPS6312380B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
JP10110182A 1982-06-10 1982-06-10 半導体装置の製造方法 Granted JPS58216437A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10110182A JPS58216437A (ja) 1982-06-10 1982-06-10 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10110182A JPS58216437A (ja) 1982-06-10 1982-06-10 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS58216437A true JPS58216437A (ja) 1983-12-16
JPS6312380B2 JPS6312380B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1988-03-18

Family

ID=14291692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10110182A Granted JPS58216437A (ja) 1982-06-10 1982-06-10 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS58216437A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006147951A (ja) * 2004-11-22 2006-06-08 Matsushita Electric Ind Co Ltd ショットキーバリアダイオード及びそれを用いた集積回路

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5429573A (en) * 1977-08-10 1979-03-05 Hitachi Ltd Fine machining method of semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5429573A (en) * 1977-08-10 1979-03-05 Hitachi Ltd Fine machining method of semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006147951A (ja) * 2004-11-22 2006-06-08 Matsushita Electric Ind Co Ltd ショットキーバリアダイオード及びそれを用いた集積回路

Also Published As

Publication number Publication date
JPS6312380B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1988-03-18

Similar Documents

Publication Publication Date Title
JPS63193562A (ja) バイポ−ラトランジスタの製造方法
EP0055521A1 (en) Method of filling a groove in a semiconductor substrate
JPH03129818A (ja) 半導体装置の製造方法
JPH02277253A (ja) 半導体装置の製造方法
JPH01130542A (ja) 素子間分離領域を有する半導体装置の製造方法
JPS58216437A (ja) 半導体装置の製造方法
JPH10308448A (ja) 半導体デバイスの隔離膜及びその形成方法
JPS62190847A (ja) 半導体装置の製造方法
JPS59124142A (ja) 半導体装置の製造方法
JPS60105247A (ja) 半導体装置の製造方法
JPS62120040A (ja) 半導体装置の製造方法
JPS6025247A (ja) 半導体装置の製造方法
JP2775782B2 (ja) 半導体装置の製造方法
KR100245087B1 (ko) 반도체소자의 소자분리절연막 형성방법
JPS6037614B2 (ja) 半導体装置の製造方法
JPS62254444A (ja) 半導体装置の製造方法
JPS63245939A (ja) 半導体装置
JPH0680726B2 (ja) 半導体装置の製造方法
JPS6236390B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH04340744A (ja) 半導体装置の製造方法
JPS63144543A (ja) 半導体素子間分離領域の形成方法
JPH0212942A (ja) 半導体装置の製造方法
JPS605072B2 (ja) 絶縁ゲ−ト型電界効果半導体装置の製造方法
JPH11340326A (ja) 半導体装置の製造方法
JPS5839026A (ja) 半導体装置及びその製造方法