JPS58211252A - 全加算器 - Google Patents

全加算器

Info

Publication number
JPS58211252A
JPS58211252A JP57095395A JP9539582A JPS58211252A JP S58211252 A JPS58211252 A JP S58211252A JP 57095395 A JP57095395 A JP 57095395A JP 9539582 A JP9539582 A JP 9539582A JP S58211252 A JPS58211252 A JP S58211252A
Authority
JP
Japan
Prior art keywords
signal
circuit
mos
exclusive
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57095395A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0215087B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Kazuo Suganuma
菅沼　一雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57095395A priority Critical patent/JPS58211252A/ja
Priority to EP83105345A priority patent/EP0096333B1/en
Priority to DE8383105345T priority patent/DE3381523D1/de
Priority to US06/499,872 priority patent/US4564921A/en
Publication of JPS58211252A publication Critical patent/JPS58211252A/ja
Publication of JPH0215087B2 publication Critical patent/JPH0215087B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
JP57095395A 1982-06-03 1982-06-03 全加算器 Granted JPS58211252A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP57095395A JPS58211252A (ja) 1982-06-03 1982-06-03 全加算器
EP83105345A EP0096333B1 (en) 1982-06-03 1983-05-30 Full adder
DE8383105345T DE3381523D1 (de) 1982-06-03 1983-05-30 Volladdierer.
US06/499,872 US4564921A (en) 1982-06-03 1983-06-01 Full adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57095395A JPS58211252A (ja) 1982-06-03 1982-06-03 全加算器

Publications (2)

Publication Number Publication Date
JPS58211252A true JPS58211252A (ja) 1983-12-08
JPH0215087B2 JPH0215087B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-04-11

Family

ID=14136459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57095395A Granted JPS58211252A (ja) 1982-06-03 1982-06-03 全加算器

Country Status (4)

Country Link
US (1) US4564921A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0096333B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS58211252A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3381523D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61276024A (ja) * 1985-05-31 1986-12-06 Toshiba Corp 全加算器
US4718035A (en) * 1984-05-24 1988-01-05 Kabushiki Kaisha Toshiba Logic operation circuit having an exclusive-OR circuit
US4831579A (en) * 1984-05-24 1989-05-16 Kabushiki Kaisha Toshiba Full adder circuit having an exclusive-OR circuit
US5920498A (en) * 1996-08-29 1999-07-06 Fujitsu Limited Compression circuit of an adder circuit

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3373566D1 (en) * 1983-04-15 1987-10-15 Itt Ind Gmbh Deutsche Cmos - full binary adder
JPS59211138A (ja) * 1983-05-16 1984-11-29 Toshiba Corp 全加算回路
JPS60134932A (ja) * 1983-12-24 1985-07-18 Toshiba Corp プリチヤ−ジ型の桁上げ連鎖加算回路
NL8400408A (nl) * 1984-02-09 1985-09-02 Philips Nv Logische optelschakeling.
US4704701A (en) * 1984-11-01 1987-11-03 Raytheon Company Conditional carry adder for a multibit digital computer
US4718034A (en) * 1984-11-08 1988-01-05 Data General Corporation Carry-save propagate adder
US4709346A (en) * 1985-04-01 1987-11-24 Raytheon Company CMOS subtractor
DE3687778D1 (en) * 1985-09-30 1993-03-25 Siemens Ag Addierzelle fuer carry-ripple-addierer in cmos-technik.
DE3687408D1 (de) * 1985-09-30 1993-02-11 Siemens Ag Mehrstelliger carry-ripple-addierer in cmos-technik mit zwei typen von addiererzellen.
JPH0619701B2 (ja) * 1985-10-31 1994-03-16 日本電気株式会社 半加算回路
JPH07104774B2 (ja) * 1985-11-26 1995-11-13 株式会社東芝 同期式演算回路
US4739503A (en) * 1986-04-21 1988-04-19 Rca Corporation Carry/borrow propagate adder/subtractor
DE3630605A1 (de) * 1986-09-09 1988-03-17 Lueder Ernst Prof Dr Ing Cmos-halbleiteranordnung als exor-nor-schaltung, insbesondere als baustein fuer eine cmos-volladdierstufe
FR2620839B2 (fr) * 1987-03-18 1991-01-18 France Etat Dispositif de calcul binaire a entrees perfectionnees
FR2612660B1 (fr) * 1987-03-18 1990-10-19 Hmida Hedi Dispositif de calcul binaire
IT1210751B (it) * 1987-05-20 1989-09-20 Cselt Centro Studi Lab Telecom Sommatore veloce in tecnologia c mos
IT1210765B (it) * 1987-05-27 1989-09-20 Cselt Centro Studi Lab Telecom Unita logico aritmetica in tecnologia c mos
DE3880409T2 (de) * 1987-09-23 1993-11-25 France Telecom Binäre Additions- und Multiplikationsvorrichtung.
EP0333884B1 (de) * 1988-03-19 1994-06-08 Deutsche ITT Industries GmbH CMOS-Parallel-Serien-Multiplizierschaltung sowie deren Multiplizier- und Addierstufen
US4899305A (en) * 1988-06-15 1990-02-06 National Semiconductor Corp. Manchester carry adder circuit
US5875124A (en) * 1995-02-22 1999-02-23 Texas Instruments Japan Ltd. Full adder circuit
US6356112B1 (en) 2000-03-28 2002-03-12 Translogic Technology, Inc. Exclusive or/nor circuit
US7185042B1 (en) * 2001-11-09 2007-02-27 National Semiconductor Corporation High speed, universal polarity full adder which consumes minimal power and minimal area
US7260595B2 (en) 2002-12-23 2007-08-21 Arithmatica Limited Logic circuit and method for carry and sum generation and method of designing such a logic circuit
US7170317B2 (en) * 2003-05-23 2007-01-30 Arithmatica Limited Sum bit generation circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5331927A (en) * 1976-09-06 1978-03-25 Nippon Telegr & Teleph Corp <Ntt> Logical sum circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5013068B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1970-07-31 1975-05-16
US3767906A (en) * 1972-01-21 1973-10-23 Rca Corp Multifunction full adder
JPS5841533B2 (ja) * 1975-10-31 1983-09-13 日本電気株式会社 ゼンカゲンサンカイロ

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5331927A (en) * 1976-09-06 1978-03-25 Nippon Telegr & Teleph Corp <Ntt> Logical sum circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4718035A (en) * 1984-05-24 1988-01-05 Kabushiki Kaisha Toshiba Logic operation circuit having an exclusive-OR circuit
US4831579A (en) * 1984-05-24 1989-05-16 Kabushiki Kaisha Toshiba Full adder circuit having an exclusive-OR circuit
JPS61276024A (ja) * 1985-05-31 1986-12-06 Toshiba Corp 全加算器
US5920498A (en) * 1996-08-29 1999-07-06 Fujitsu Limited Compression circuit of an adder circuit
US6240438B1 (en) 1996-08-29 2001-05-29 Fujitsu Limited Multiplier circuit for reducing the number of necessary elements without sacrificing high speed capability
US6535902B2 (en) 1996-08-29 2003-03-18 Fujitsu Limited Multiplier circuit for reducing the number of necessary elements without sacrificing high speed capability

Also Published As

Publication number Publication date
EP0096333A2 (en) 1983-12-21
US4564921A (en) 1986-01-14
JPH0215087B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-04-11
DE3381523D1 (de) 1990-06-07
EP0096333A3 (en) 1986-02-05
EP0096333B1 (en) 1990-05-02

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