DE3381523D1 - Volladdierer. - Google Patents

Volladdierer.

Info

Publication number
DE3381523D1
DE3381523D1 DE8383105345T DE3381523T DE3381523D1 DE 3381523 D1 DE3381523 D1 DE 3381523D1 DE 8383105345 T DE8383105345 T DE 8383105345T DE 3381523 T DE3381523 T DE 3381523T DE 3381523 D1 DE3381523 D1 DE 3381523D1
Authority
DE
Germany
Prior art keywords
full adders
adders
full
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8383105345T
Other languages
English (en)
Inventor
Kazuo Suganuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3381523D1 publication Critical patent/DE3381523D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
DE8383105345T 1982-06-03 1983-05-30 Volladdierer. Expired - Lifetime DE3381523D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57095395A JPS58211252A (ja) 1982-06-03 1982-06-03 全加算器

Publications (1)

Publication Number Publication Date
DE3381523D1 true DE3381523D1 (de) 1990-06-07

Family

ID=14136459

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383105345T Expired - Lifetime DE3381523D1 (de) 1982-06-03 1983-05-30 Volladdierer.

Country Status (4)

Country Link
US (1) US4564921A (de)
EP (1) EP0096333B1 (de)
JP (1) JPS58211252A (de)
DE (1) DE3381523D1 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0122946B1 (de) * 1983-04-15 1987-09-09 Deutsche ITT Industries GmbH CMOS-Volladdierstufe
JPS59211138A (ja) * 1983-05-16 1984-11-29 Toshiba Corp 全加算回路
JPS60134932A (ja) * 1983-12-24 1985-07-18 Toshiba Corp プリチヤ−ジ型の桁上げ連鎖加算回路
NL8400408A (nl) * 1984-02-09 1985-09-02 Philips Nv Logische optelschakeling.
JPS60247734A (ja) * 1984-05-24 1985-12-07 Toshiba Corp 論理演算回路
JPS60247733A (ja) * 1984-05-24 1985-12-07 Toshiba Corp 論理演算回路
US4704701A (en) * 1984-11-01 1987-11-03 Raytheon Company Conditional carry adder for a multibit digital computer
US4718034A (en) * 1984-11-08 1988-01-05 Data General Corporation Carry-save propagate adder
US4709346A (en) * 1985-04-01 1987-11-24 Raytheon Company CMOS subtractor
JPS61276024A (ja) * 1985-05-31 1986-12-06 Toshiba Corp 全加算器
EP0218071B1 (de) * 1985-09-30 1993-02-17 Siemens Aktiengesellschaft Addierzelle für Carry-Ripple-Addierer in CMOS-Technik
ATE84155T1 (de) * 1985-09-30 1993-01-15 Siemens Ag Mehrstelliger carry-ripple-addierer in cmostechnik mit zwei typen von addiererzellen.
JPH0619701B2 (ja) * 1985-10-31 1994-03-16 日本電気株式会社 半加算回路
JPH07104774B2 (ja) * 1985-11-26 1995-11-13 株式会社東芝 同期式演算回路
US4739503A (en) * 1986-04-21 1988-04-19 Rca Corporation Carry/borrow propagate adder/subtractor
DE3630605A1 (de) * 1986-09-09 1988-03-17 Lueder Ernst Prof Dr Ing Cmos-halbleiteranordnung als exor-nor-schaltung, insbesondere als baustein fuer eine cmos-volladdierstufe
FR2620839B2 (fr) * 1987-03-18 1991-01-18 France Etat Dispositif de calcul binaire a entrees perfectionnees
FR2612660B1 (fr) * 1987-03-18 1990-10-19 Hmida Hedi Dispositif de calcul binaire
IT1210751B (it) * 1987-05-20 1989-09-20 Cselt Centro Studi Lab Telecom Sommatore veloce in tecnologia c mos
IT1210765B (it) * 1987-05-27 1989-09-20 Cselt Centro Studi Lab Telecom Unita logico aritmetica in tecnologia c mos
EP0309348B1 (de) * 1987-09-23 1993-04-21 France Telecom Binäre Additions- und Multiplikationsvorrichtung
EP0333884B1 (de) * 1988-03-19 1994-06-08 Deutsche ITT Industries GmbH CMOS-Parallel-Serien-Multiplizierschaltung sowie deren Multiplizier- und Addierstufen
US4899305A (en) * 1988-06-15 1990-02-06 National Semiconductor Corp. Manchester carry adder circuit
US5875124A (en) * 1995-02-22 1999-02-23 Texas Instruments Japan Ltd. Full adder circuit
JP3678512B2 (ja) 1996-08-29 2005-08-03 富士通株式会社 乗算回路、該乗算回路を構成する加算回路、該乗算回路の部分積ビット圧縮方法、および、該乗算回路を適用した大規模半導体集積回路
US6356112B1 (en) 2000-03-28 2002-03-12 Translogic Technology, Inc. Exclusive or/nor circuit
US7185042B1 (en) * 2001-11-09 2007-02-27 National Semiconductor Corporation High speed, universal polarity full adder which consumes minimal power and minimal area
GB2396718B (en) 2002-12-23 2005-07-13 Arithmatica Ltd A logic circuit and method for carry and sum generation and method of designing such a logic circuit
WO2004104820A2 (en) * 2003-05-23 2004-12-02 Arithmatica Limited A sum bit generation circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5013068B1 (de) * 1970-07-31 1975-05-16
US3767906A (en) * 1972-01-21 1973-10-23 Rca Corp Multifunction full adder
JPS5841533B2 (ja) * 1975-10-31 1983-09-13 日本電気株式会社 ゼンカゲンサンカイロ
JPS5331927A (en) * 1976-09-06 1978-03-25 Nippon Telegr & Teleph Corp <Ntt> Logical sum circuit

Also Published As

Publication number Publication date
EP0096333A3 (en) 1986-02-05
JPS58211252A (ja) 1983-12-08
US4564921A (en) 1986-01-14
JPH0215087B2 (de) 1990-04-11
EP0096333A2 (de) 1983-12-21
EP0096333B1 (de) 1990-05-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee