JPS5793730A - Signal level conversion circuit - Google Patents
Signal level conversion circuitInfo
- Publication number
- JPS5793730A JPS5793730A JP55169625A JP16962580A JPS5793730A JP S5793730 A JPS5793730 A JP S5793730A JP 55169625 A JP55169625 A JP 55169625A JP 16962580 A JP16962580 A JP 16962580A JP S5793730 A JPS5793730 A JP S5793730A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- applying
- conversion circuit
- level conversion
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Abstract
PURPOSE:To make circuit connection easy, by performing the connection between elements different in power supply voltage with one level conversion circuit, in IC logical circuits such as a DTL, a TTL and a CMOS and the like. CONSTITUTION:An FET9 is conductive by applying a gate voltage VS1 for FET driving control and an FET10 is nonconductive by not applying a gate voltage VS2 for FET driving control, and a slide terminal voltage VE1 of a variable resistor 7 is selected as a reference voltage of an operational amplifier 6, and the level comparison between the reference voltage VE1 and an input voltage VIN is made at the operational amplifier 6. A logical operation taking a VE2 as the reference voltage can be made by applying the gate voltage of VS2 only to conduct the FET10 and to unconduct the FET9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55169625A JPS5793730A (en) | 1980-12-03 | 1980-12-03 | Signal level conversion circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55169625A JPS5793730A (en) | 1980-12-03 | 1980-12-03 | Signal level conversion circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5793730A true JPS5793730A (en) | 1982-06-10 |
Family
ID=15889966
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55169625A Pending JPS5793730A (en) | 1980-12-03 | 1980-12-03 | Signal level conversion circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5793730A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01106926U (en) * | 1987-12-29 | 1989-07-19 | ||
CN108282161A (en) * | 2018-01-25 | 2018-07-13 | 郑州云海信息技术有限公司 | A kind of reduction regulation circuit of automatic adjustment working frequency |
-
1980
- 1980-12-03 JP JP55169625A patent/JPS5793730A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01106926U (en) * | 1987-12-29 | 1989-07-19 | ||
JPH0441384Y2 (en) * | 1987-12-29 | 1992-09-29 | ||
CN108282161A (en) * | 2018-01-25 | 2018-07-13 | 郑州云海信息技术有限公司 | A kind of reduction regulation circuit of automatic adjustment working frequency |
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