JPS5461433A - Tri-value converter circuit - Google Patents

Tri-value converter circuit

Info

Publication number
JPS5461433A
JPS5461433A JP12829777A JP12829777A JPS5461433A JP S5461433 A JPS5461433 A JP S5461433A JP 12829777 A JP12829777 A JP 12829777A JP 12829777 A JP12829777 A JP 12829777A JP S5461433 A JPS5461433 A JP S5461433A
Authority
JP
Japan
Prior art keywords
fet
terminal
conductive
fed
tri
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12829777A
Other languages
Japanese (ja)
Other versions
JPS5633896B2 (en
Inventor
Yasoji Suzuki
Ryuzo Shiraki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12829777A priority Critical patent/JPS5461433A/en
Priority to US05/941,256 priority patent/US4217502A/en
Publication of JPS5461433A publication Critical patent/JPS5461433A/en
Publication of JPS5633896B2 publication Critical patent/JPS5633896B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Power Engineering (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To improve the leading time of the output voltage, by providing the circuit covering the reduction in the output current against IF-FET and by constituting the circuit so that it can rapidly be conducted. CONSTITUTION:When + 10V is fed to the tri-value control signal terminal 4, the output of the NOR circuit 24 is O volt, causing non-conduction to FET 23 and FET 21, and the output terminal 9 is of high impedance. Further, when O V is fed to the terminal 4, the output of the circuit 24 IN, and when OV is fed to the input signal terminal 1, causing FET 23 conductive and FET22 non-conductive, and the terminal 9 is O V. Further, when + 10 V is fed to the terminal 1, FET 21 and 22 are conductive and the output voltage is + 10 V. Then, since the tri-value control signal EN is + 10V with the high impedance state in taking tri-value level, FET 41 is non-conductive and FET 42 is made non-conductive in conducting FET 23. On the other hand, when + 10V is fed to the terminal 1 and O V is fed to the terminal 4 respectively, FET 42 is immediately conductive. Further, FET 41 is also conductive via the inverter 43.
JP12829777A 1977-09-10 1977-10-26 Tri-value converter circuit Granted JPS5461433A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP12829777A JPS5461433A (en) 1977-10-26 1977-10-26 Tri-value converter circuit
US05/941,256 US4217502A (en) 1977-09-10 1978-09-11 Converter producing three output states

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12829777A JPS5461433A (en) 1977-10-26 1977-10-26 Tri-value converter circuit

Publications (2)

Publication Number Publication Date
JPS5461433A true JPS5461433A (en) 1979-05-17
JPS5633896B2 JPS5633896B2 (en) 1981-08-06

Family

ID=14981307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12829777A Granted JPS5461433A (en) 1977-09-10 1977-10-26 Tri-value converter circuit

Country Status (1)

Country Link
JP (1) JPS5461433A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5975721A (en) * 1982-10-25 1984-04-28 Toshiba Corp Signal input circuit and its controlling method
JPS614325A (en) * 1984-06-19 1986-01-10 Nec Corp Complementary integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5975721A (en) * 1982-10-25 1984-04-28 Toshiba Corp Signal input circuit and its controlling method
JPH0446013B2 (en) * 1982-10-25 1992-07-28 Tokyo Shibaura Electric Co
JPS614325A (en) * 1984-06-19 1986-01-10 Nec Corp Complementary integrated circuit

Also Published As

Publication number Publication date
JPS5633896B2 (en) 1981-08-06

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Legal Events

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A131 Notification of reasons for refusal

Effective date: 20070821

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A313 Final decision of rejection without a dissenting response from the applicant

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A02 Decision of refusal

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