JPS5711537A - Logical circuit - Google Patents
Logical circuitInfo
- Publication number
- JPS5711537A JPS5711537A JP8630780A JP8630780A JPS5711537A JP S5711537 A JPS5711537 A JP S5711537A JP 8630780 A JP8630780 A JP 8630780A JP 8630780 A JP8630780 A JP 8630780A JP S5711537 A JPS5711537 A JP S5711537A
- Authority
- JP
- Japan
- Prior art keywords
- level
- node
- output
- power supply
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 abstract 4
- 230000003247 decreasing Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
- 230000005669 field effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back
Abstract
PURPOSE:To pull up an output to a power supply level at all time, against any input condition, by using a bootstrap capacitor for a logical circuit using a field effect transistor (TR) and pulling up the output to the power supply level. CONSTITUTION:An input waveform A is inputted to inverters Q1, Q2 and also FETs Q3, Q4, and the output of the FETs Q3, Q4 is applied to a bootstrap capacitor C1. When the input level is fallen down after being once up, since the level of a node 3 is already down to caused high impedance FET Q3 and the FET Q4 is nonconductive based on the lower level of an output terminal B, the level of the node 1 in not decreased. Thus, the electric charge stored in the capacitor C1 is not lost, the node 1 is pulled up more than the power supply level, resulting in increasing the output B to the power supply level. Even if the input level is fallen down until the level of the node 3 is not fallen down, the FET Q3 is conductive and the node 4 is at gronded level, and the capacitor C1 enables bootstrap effect.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8630780A JPS5711537A (en) | 1980-06-25 | 1980-06-25 | Logical circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8630780A JPS5711537A (en) | 1980-06-25 | 1980-06-25 | Logical circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5711537A true JPS5711537A (en) | 1982-01-21 |
Family
ID=13883170
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8630780A Pending JPS5711537A (en) | 1980-06-25 | 1980-06-25 | Logical circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5711537A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4556779A (en) * | 1982-03-18 | 1985-12-03 | Minolta Camera Kabushiki Kaisha | Temperature control arrangement for heat roller |
US5369320A (en) * | 1992-07-22 | 1994-11-29 | Oki Electric Industry Co., Ltd. | Bootstrapped high-speed output buffer |
-
1980
- 1980-06-25 JP JP8630780A patent/JPS5711537A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4556779A (en) * | 1982-03-18 | 1985-12-03 | Minolta Camera Kabushiki Kaisha | Temperature control arrangement for heat roller |
US5369320A (en) * | 1992-07-22 | 1994-11-29 | Oki Electric Industry Co., Ltd. | Bootstrapped high-speed output buffer |
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