JPS5679522A - Cmos schmitt trigger circuit - Google Patents

Cmos schmitt trigger circuit

Info

Publication number
JPS5679522A
JPS5679522A JP15616379A JP15616379A JPS5679522A JP S5679522 A JPS5679522 A JP S5679522A JP 15616379 A JP15616379 A JP 15616379A JP 15616379 A JP15616379 A JP 15616379A JP S5679522 A JPS5679522 A JP S5679522A
Authority
JP
Japan
Prior art keywords
inverter
voltage
output
output voltage
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15616379A
Other languages
Japanese (ja)
Inventor
Masahiro Mikami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP15616379A priority Critical patent/JPS5679522A/en
Publication of JPS5679522A publication Critical patent/JPS5679522A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger

Abstract

PURPOSE:To form the Schmitt trigger circuit having the hysteresis characteristics for the input and output characteristics with a simple circuit constitution, by using C- MOS inverters of cascade connection and one MOSFET for feedback. CONSTITUTION:When an input voltage V3 is a low voltage VSS, the output voltage V4 is a high voltage VDD. When the input voltage V3 is increased, the output voltage V4 is lowered. In this case, a transistor 13 is the load of an inverter 18 and the output voltage V4 is further lowered. This is amplified at an inverter 19 and appears at the terminal 17. Then, the transistor 13 is more conductive, resulting that the output voltage V4 is further lowered. When the input voltage V3 is increased, the output voltage V4 of the inverter 18 is increased. This is amplified at the inverter 19 to make nonconductive the transistor 13. As a result, the output of the inverter 19 is more strongly lowered.
JP15616379A 1979-11-30 1979-11-30 Cmos schmitt trigger circuit Pending JPS5679522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15616379A JPS5679522A (en) 1979-11-30 1979-11-30 Cmos schmitt trigger circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15616379A JPS5679522A (en) 1979-11-30 1979-11-30 Cmos schmitt trigger circuit

Publications (1)

Publication Number Publication Date
JPS5679522A true JPS5679522A (en) 1981-06-30

Family

ID=15621720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15616379A Pending JPS5679522A (en) 1979-11-30 1979-11-30 Cmos schmitt trigger circuit

Country Status (1)

Country Link
JP (1) JPS5679522A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0085991A2 (en) * 1982-02-10 1983-08-17 Nec Corporation Logic circuit
EP1091491A1 (en) * 1999-09-15 2001-04-11 Infineon Technologies AG Input buffer for integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5480058A (en) * 1977-12-09 1979-06-26 Hitachi Ltd Schmitt trigger circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5480058A (en) * 1977-12-09 1979-06-26 Hitachi Ltd Schmitt trigger circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0085991A2 (en) * 1982-02-10 1983-08-17 Nec Corporation Logic circuit
EP1091491A1 (en) * 1999-09-15 2001-04-11 Infineon Technologies AG Input buffer for integrated circuit
US6480039B1 (en) 1999-09-15 2002-11-12 Infineon Technologies Ag Input buffer of an integrated semiconductor circuit

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