JPS5784158A - Lead frame and its manufacture - Google Patents

Lead frame and its manufacture

Info

Publication number
JPS5784158A
JPS5784158A JP55161176A JP16117680A JPS5784158A JP S5784158 A JPS5784158 A JP S5784158A JP 55161176 A JP55161176 A JP 55161176A JP 16117680 A JP16117680 A JP 16117680A JP S5784158 A JPS5784158 A JP S5784158A
Authority
JP
Japan
Prior art keywords
lead frame
metal layer
slit
region
adhesing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55161176A
Other languages
Japanese (ja)
Other versions
JPS6050355B2 (en
Inventor
Masami Yokozawa
Hiroyuki Fujii
Kenichi Tateno
Misao Katou
Mikio Nishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP55161176A priority Critical patent/JPS6050355B2/en
Publication of JPS5784158A publication Critical patent/JPS5784158A/en
Publication of JPS6050355B2 publication Critical patent/JPS6050355B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent deterioration of insulating characteristics in the case of cutting a lead frame by a method wherein a semiconductor supporting region of a lead frame is built as a three-layered structure with an intermediary of an insulating layer, and a slit is provided in the first metal layer. CONSTITUTION:In a lead frame which consists of the first metal layer which forms a supporting region for semiconductor substrate provided with a slit 17, and the second metal layer 14 with an intermediary of an insulating layer 13 which can not be deteriorated in electrical insulation in spite of heat-treatment such as polyimide resin or the like, the fore-mentioned slit 17 divides into two regions of an adhesing region 61 for a semiconductor substrate and a not-adhesing region 62 in this structure. By this constitution, even though there exist shortcircuiting fault between the first metal layer 12 and the second metal layer 14 by burrs to be generated at the time of cutting the lead frame, shortcircuiting does not take place because of electrical segregation at the slit.
JP55161176A 1980-11-14 1980-11-14 Lead frame and its manufacturing method Expired JPS6050355B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55161176A JPS6050355B2 (en) 1980-11-14 1980-11-14 Lead frame and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55161176A JPS6050355B2 (en) 1980-11-14 1980-11-14 Lead frame and its manufacturing method

Publications (2)

Publication Number Publication Date
JPS5784158A true JPS5784158A (en) 1982-05-26
JPS6050355B2 JPS6050355B2 (en) 1985-11-08

Family

ID=15730022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55161176A Expired JPS6050355B2 (en) 1980-11-14 1980-11-14 Lead frame and its manufacturing method

Country Status (1)

Country Link
JP (1) JPS6050355B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002274783A (en) * 2001-03-19 2002-09-25 Furukawa Co Ltd Outrigger device for on-vehicle crane

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0622761U (en) * 1992-04-21 1994-03-25 有限会社ウルトラモダンエクウィップメント Disposable lighter case

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002274783A (en) * 2001-03-19 2002-09-25 Furukawa Co Ltd Outrigger device for on-vehicle crane

Also Published As

Publication number Publication date
JPS6050355B2 (en) 1985-11-08

Similar Documents

Publication Publication Date Title
JPS6451665A (en) Semiconductor device
JPS56161668A (en) Semiconductor device
JPS5784158A (en) Lead frame and its manufacture
JPS5693359A (en) Semiconductor integrated circuit and manufacture
JPS5784156A (en) Lead frame and its manufacture
JPS6445147A (en) Semiconductor device
JPS56150865A (en) Insulated gate type field effect semiconductor device
JPS5552252A (en) Semiconductor integrated circuit device and manufacturing of them
JPS5662382A (en) Hall element
JPS6445142A (en) Semiconductor device
JPS6457664A (en) Contact connection structure
JPS5740973A (en) Inverter circuit and manufacture therefor
JPS57104252A (en) Polycrystal silicon-fuse-memory and its manufacture
JPS57194582A (en) Semiconductor integrated circuit device and manufacture thereof
JPS5624939A (en) Manufacture of semiconductor device
JPS57190333A (en) Semiconductor device
JPS57183050A (en) Integrated circuit
JPS57170570A (en) Field effect transistor
JPS56157038A (en) Manufacture of semiconductor device
JPS6410647A (en) Manufacture of semiconductor device
JPS6464361A (en) Semiconductor device
JPS574141A (en) Wiring structure in semiconductor device
JPS56167347A (en) Semiconductor device
JPS567451A (en) Semiconductor device
JPS52151572A (en) Insulated gate semiconductor device and its production