JPS56167347A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS56167347A JPS56167347A JP7118480A JP7118480A JPS56167347A JP S56167347 A JPS56167347 A JP S56167347A JP 7118480 A JP7118480 A JP 7118480A JP 7118480 A JP7118480 A JP 7118480A JP S56167347 A JPS56167347 A JP S56167347A
- Authority
- JP
- Japan
- Prior art keywords
- type
- regions
- highly concentrated
- conductive type
- type regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
PURPOSE:To prevent the generation of parasitic MOS effect in the semiconductor device by a method wherein the other conductive type region formed in a one conductive type substrate is surrounded with the one conductive type highly concentrated regions and other conductive type regions or wiring layers connected to the one conductive type highly concentrated regions. CONSTITUTION:For example, in the structure being provided with the reversely biased P type regions 11, 13 in the N type substrate 17, and being arranged with an Al wiring 14 between those regions interposing an insulating film between them, the highly concentrated N type regions 12 are provided as channel blocking layers on both sides of the P type region 11. The Al wirings 15, 16 to be connected to the P type region 11 are positioned at both ends of the N type regions 12, for example, as to surround the P type region 11 with the N type regions 12 and the wirings 15, 16. Accordingly a leak current to be generated between the P type regions 11, 13 can be prevented completely even when the oxide film is electrically charged because of contamination, etc. Moreover because channel blocking effect can be obtained without extending the highly concentrated N type regions expressely, enhancement of integration can be realized.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7118480A JPS56167347A (en) | 1980-05-28 | 1980-05-28 | Semiconductor device |
| GB8116291A GB2080617B (en) | 1980-05-28 | 1981-05-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7118480A JPS56167347A (en) | 1980-05-28 | 1980-05-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56167347A true JPS56167347A (en) | 1981-12-23 |
| JPS6322066B2 JPS6322066B2 (en) | 1988-05-10 |
Family
ID=13453307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7118480A Granted JPS56167347A (en) | 1980-05-28 | 1980-05-28 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS56167347A (en) |
| GB (1) | GB2080617B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5023791A (en) * | 1973-06-30 | 1975-03-14 |
-
1980
- 1980-05-28 JP JP7118480A patent/JPS56167347A/en active Granted
-
1981
- 1981-05-28 GB GB8116291A patent/GB2080617B/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5023791A (en) * | 1973-06-30 | 1975-03-14 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6322066B2 (en) | 1988-05-10 |
| GB2080617B (en) | 1984-09-26 |
| GB2080617A (en) | 1982-02-03 |
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