JPS6322066B2 - - Google Patents
Info
- Publication number
- JPS6322066B2 JPS6322066B2 JP55071184A JP7118480A JPS6322066B2 JP S6322066 B2 JPS6322066 B2 JP S6322066B2 JP 55071184 A JP55071184 A JP 55071184A JP 7118480 A JP7118480 A JP 7118480A JP S6322066 B2 JPS6322066 B2 JP S6322066B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- regions
- region
- type
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 13
- 229910052782 aluminium Inorganic materials 0.000 description 13
- 230000000694 effects Effects 0.000 description 12
- 230000003071 parasitic effect Effects 0.000 description 9
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置、特に寄生MOS効果を防
止する構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a structure for preventing parasitic MOS effects.
半導体集積回路において、Ｎ形基板中の逆バイ
アスされた２つ以上の隣接するＰ形領域間の上を
酸化膜を介してアルミ配線が置かれている場合、
アルミ配線に加わる電位によつてその下にチヤン
ネルが生じてＰ形領域相互間に電流が流れること
がある。この作用を積極的に利用したのがMOS
形電界効果トランジスタであるが、この作用が単
なる配線層の下で生じて絶縁されているべき領域
同志が導通する現象を寄生MOS効果という。通
常この寄生MOS効果を防止したい場合は、第１
図のように、Ｎ型基板に形成された所定のＰ形領
域の間にチヤンネルストツパーと呼ぶ高濃度のＮ
形領域を設けることがなされている。 In a semiconductor integrated circuit, when aluminum wiring is placed between two or more adjacent reverse-biased P-type regions in an N-type substrate via an oxide film,
The potential applied to the aluminum wiring may create a channel beneath it, allowing current to flow between the P-type regions. MOS actively utilized this effect.
Although it is a type field effect transistor, the phenomenon in which this effect occurs under a simple wiring layer and conducts between regions that should be insulated is called the parasitic MOS effect. Normally, if you want to prevent this parasitic MOS effect, the first
As shown in the figure, a high concentration of N, called a channel stopper, is placed between predetermined P-type regions formed on an N-type substrate.
A shape area is provided.
しかしながら酸化膜表面の汚れや水分等が付着
した場合は汚れや水分に電荷がたまり、これらが
新たなゲート電極として働くためアルミ配線のな
い所にも寄生MOS効果が生じ、このため、単に
アルミ配線の下にのみ高濃度Ｎ形領域を設けても
この寄生MOS効果を防ぐことができない。 However, if dirt or moisture adheres to the surface of the oxide film, charges accumulate on the dirt or moisture, and these act as new gate electrodes, creating a parasitic MOS effect even where there is no aluminum wiring. This parasitic MOS effect cannot be prevented even if a heavily doped N-type region is provided only under the MOS transistor.
また高濃度Ｎ型領域で一方のＰ型領域を囲んで
しまうと、このような場合の寄生MOS効果も防
止できるが、この高濃度Ｎ型領域の占有面積が増
すばかりでなく他のＰ型領域との間にも十分な間
隔を設けねばならないので高密度な集積回路が得
られないという欠点がある。 Furthermore, if one P-type region is surrounded by a highly doped N-type region, the parasitic MOS effect in such a case can be prevented, but not only does the area occupied by this highly doped N-type region increase, but also the other P-type region Since a sufficient space must also be provided between the two, there is a drawback that a high-density integrated circuit cannot be obtained.
本発明の目的はかかる従来のチヤンネルストツ
パーを改善し、小さい占有面積で効果のあるチヤ
ンネルストツパーを提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to improve such a conventional channel stopper and to provide an effective channel stopper that occupies a small area.
本発明によれば、一導電形の半導体基体に形成
された他の導電形の半導体領域を一導電形の高濃
度領域と前記の他の導電形の半導体領域又は一導
電形の高濃度領域に接続された配線層で取り囲
み、一導電形の高濃度領域上に他の配線層を配し
た半導体装置を得る。 According to the present invention, a semiconductor region of another conductivity type formed in a semiconductor substrate of one conductivity type is combined with a high concentration region of one conductivity type and the semiconductor region of the other conductivity type or a high concentration region of one conductivity type. A semiconductor device is obtained in which a high concentration region of one conductivity type is surrounded by connected wiring layers and another wiring layer is placed on top of the high concentration region.
以下、本発明を図面を参照してより詳細に説明
する。 Hereinafter, the present invention will be explained in more detail with reference to the drawings.
第１図において最高電位に印加されたＮ形エピ
タキシヤル領域７の中にＰ形領域１及び３があ
り、それらの上に低電位アルミ配線４が通つてお
り各Ｐ形領域１及び３には端子５，５′，６，
６′が接続されているとき、端子５とアルミ配線
４の間にこの部分のもつ閾値電圧を越える高い電
圧が印加されるとアルミ配線４直下のエピタキシ
ヤル層７の導電型が反転してＰ型領域１と３の間
にチヤンネルができ、このチヤンネルを通して電
流が流れる。そのために、チヤンネルストツパー
として高濃度のＮ形領域２を低電位アルミ配線４
の下に置けば通常の場合寄生MOS効果のチヤン
ネルを防止できる。 In FIG. 1, there are P-type regions 1 and 3 in the N-type epitaxial region 7 to which the highest potential is applied, and a low-potential aluminum wiring 4 runs above them. Terminals 5, 5', 6,
6' is connected, if a high voltage exceeding the threshold voltage of this part is applied between the terminal 5 and the aluminum wiring 4, the conductivity type of the epitaxial layer 7 directly under the aluminum wiring 4 is reversed and P A channel is created between mold regions 1 and 3, through which current flows. For this purpose, the high concentration N-type region 2 is used as a channel stopper for the low potential aluminum wiring 4.
Under normal circumstances, channels of parasitic MOS effects can be prevented.
しかしながら酸化膜表面が汚れたり水分が付着
した場合には、アルミ配線４から電荷が流出して
これら汚れや水分が帯電し、その下にチヤンネル
を形成することがあり、このため、低電位アルミ
配線４の下にのみチヤンネルストツパー２を置い
てもＰ形領域１，３の間の寄生MOS効果は防止
できない。 However, if the surface of the oxide film gets dirty or moisture adheres to it, the electric charge flows out from the aluminum wiring 4, and these dirt and moisture become charged and may form a channel underneath. Even if the channel stopper 2 is placed only under the P-type regions 1 and 3, the parasitic MOS effect between the P-type regions 1 and 3 cannot be prevented.
このとき第２図に示すように、Ｐ形領域１の全
周をチヤンネルストツパー２′でかこめばあらゆ
る場合についてＰ形領域１と３の間のリーク電流
を防止できる。 At this time, as shown in FIG. 2, if the entire circumference of P-type region 1 is surrounded by a channel stopper 2', leakage current between P-type regions 1 and 3 can be prevented in all cases.
しかしながら、この場合チヤンネルストツパー
２′の占有面積が大きく、またその周囲には製造
工程上の位置合せ余裕のために他のＰ形領域との
間に所定の間隔を維持しなければならないため高
集積化のさまたげとなつていた。 However, in this case, the area occupied by the channel stopper 2' is large, and a predetermined distance must be maintained between the channel stopper 2' and other P-shaped regions to allow for alignment margins in the manufacturing process, so the height of the channel stopper 2' is large. This had become a hindrance to agglomeration.
本発明の一実施例を第３図に示す。Ｎ形基板１
７の中に逆バイアスされた２つのＰ形領域１１及
び１３があり、それらの間に通常は低電位が与え
られるアルミ配線１４が絶縁膜を介して置かれて
おり、これらＰ形領域１１及び１３には適当な電
極端子１５，１５′，１６，１６′が接続されてお
り、更にこのアルミ配線１４の電位と端子電位１
５及び１６の電位差がＰ形領域１１，１３とアル
ミ配線１４で形成される寄生MOSトランジスタ
の閾値電圧を越える場合にチヤンネルストツパー
として作用するように、高濃度Ｎ形領域１２をＰ
形領域１１の両側に形成し、この高濃度Ｎ形領域
１２の各両端端子１５及び１６を形成するアルミ
配線が位置するようにしてＰ形領域１１をこれら
高濃度Ｎ形領域１２と端子１５，１６で取り囲ん
でいる。 An embodiment of the present invention is shown in FIG. N type board 1
There are two reverse-biased P-type regions 11 and 13 in the P-type region 7, and an aluminum wiring 14 to which a low potential is usually applied is placed between them with an insulating film interposed therebetween. Appropriate electrode terminals 15, 15', 16, 16' are connected to 13, and the potential of this aluminum wiring 14 and the terminal potential 1
The heavily doped N-type region 12 is connected to a P-type so that it acts as a channel stopper when the potential difference between the P-type regions 11 and 16 exceeds the threshold voltage of the parasitic MOS transistor formed by the P-type regions 11 and 13 and the aluminum wiring 14.
The P-type region 11 is connected to the high-concentration N-type region 12 and the terminals 15 and 16 in such a way that the aluminum wires formed on both sides of the high-concentration N-type region 12 and forming the terminals 15 and 16 at both ends of the high-concentration N-type region 12 are located. It is surrounded by 16.
このようにすると、２つのＰ形領域１１及び１
３の間のリーク電流はたとえ帯電した水分や汚れ
があつても完全に防止できる。 In this way, two P-type regions 11 and 1
Leakage current between 3 and 3 can be completely prevented even if there is charged moisture or dirt.
本発明によれば、チヤンネルストツパーのため
の高濃度Ｎ形領域１２をいたずらにひろげる必要
はなく、小さい占有面積で絶大なチヤンネルスト
ツプ効果が得られ、より高い集積密度の集積回路
が得られる。 According to the present invention, there is no need to unnecessarily expand the highly doped N-type region 12 for channel stopper, and a tremendous channel stop effect can be obtained with a small occupied area, resulting in an integrated circuit with higher integration density. .
上記実施例ではチヤンネルストツパーとしての
基体と同一導電形の高濃度層とともに他の導電形
領域を囲む配線層を他の導電形の領域と接続した
が、他に同一導電形の高濃度層と接続して他の導
電形の領域とは分離せしめておいても同様の効果
が得られる。 In the above embodiment, a high concentration layer of the same conductivity type as the substrate as a channel stopper and a wiring layer surrounding another conductivity type region are connected to another conductivity type region, but there is also a high concentration layer of the same conductivity type. A similar effect can be obtained even if the region is connected and separated from regions of other conductivity types.
第１図は従来のチヤンネルストツパーの構造を
示す平面図、第２図は酸化膜表面の汚れや水分の
存在にも耐える他の従来のチヤンネルストツパー
の構造を示す平面図、第３図は本発明の一実施例
にかかるチヤンネルストツパーの構造を示す平面
図である。
１，３，１１，１３……Ｐ型領域、２，１２…
…高濃度Ｎ形領域、４，１４……アルミ配線、
５，５′，６，６′，１５，１６……端子、７……
Ｎ形基板。
Fig. 1 is a plan view showing the structure of a conventional channel stopper, Fig. 2 is a plan view showing the structure of another conventional channel stopper that can withstand the presence of dirt and moisture on the oxide film surface, and Fig. 3 is a plan view showing the structure of a conventional channel stopper. FIG. 2 is a plan view showing the structure of a channel stopper according to an embodiment of the present invention. 1, 3, 11, 13...P type region, 2, 12...
...High concentration N-type region, 4,14...Aluminum wiring,
5, 5', 6, 6', 15, 16... terminal, 7...
N type board.
Claims (1)
２つの他の導電型の領域と、該少くとも２つの他
の導電型の領域と交叉して該少くとも２つの他の
導電型の領域間の前記半導体基板上に絶縁膜を介
して形成された第１の配線層と、前記少くとも２
つの他の導電型の領域間の前記半導体基板表面領
域で前記第１の配線層下に形成された前記一導電
型の第１の高不純物濃度領域と、前記少くとも２
つの他の導電型の領域の一方の周辺に形成された
第２の配線層および前記一導電型の第２の高不純
物濃度領域とを有し、前記第２の配線層および前
記第１と第２の高不純物濃度領域は平面的に前記
一方の他の導電型の領域をとり囲むように配置さ
れており、さらに前記第２の配線層は前記一方の
他の導電型の領域に接続されており、かつ前記第
２の配線層と前記第１および第２の高不純物濃度
領域とは接触することなく部分的に重なり合つて
いることを特徴とする半導体装置。1 At least two regions of another conductivity type formed on a semiconductor substrate of one conductivity type, and between the at least two regions of other conductivity type that intersect with the at least two regions of other conductivity type. a first wiring layer formed on the semiconductor substrate with an insulating film interposed therebetween;
the first high impurity concentration region of one conductivity type formed under the first wiring layer in the semiconductor substrate surface region between the two other conductivity type regions;
a second wiring layer formed around one of the two other conductivity type regions and the second high impurity concentration region of the one conductivity type; The second high impurity concentration region is arranged so as to surround the one region of the other conductivity type in a plan view, and the second wiring layer is connected to the one region of the other conductivity type. and the second wiring layer and the first and second high impurity concentration regions partially overlap each other without contacting each other.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7118480A JPS56167347A (en) | 1980-05-28 | 1980-05-28 | Semiconductor device |
| GB8116291A GB2080617B (en) | 1980-05-28 | 1981-05-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7118480A JPS56167347A (en) | 1980-05-28 | 1980-05-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56167347A JPS56167347A (en) | 1981-12-23 |
| JPS6322066B2 true JPS6322066B2 (en) | 1988-05-10 |
Family
ID=13453307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7118480A Granted JPS56167347A (en) | 1980-05-28 | 1980-05-28 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS56167347A (en) |
| GB (1) | GB2080617B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5023791A (en) * | 1973-06-30 | 1975-03-14 |
-
1980
- 1980-05-28 JP JP7118480A patent/JPS56167347A/en active Granted
-
1981
- 1981-05-28 GB GB8116291A patent/GB2080617B/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5023791A (en) * | 1973-06-30 | 1975-03-14 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56167347A (en) | 1981-12-23 |
| GB2080617A (en) | 1982-02-03 |
| GB2080617B (en) | 1984-09-26 |
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