JPS57159046A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS57159046A JPS57159046A JP4378681A JP4378681A JPS57159046A JP S57159046 A JPS57159046 A JP S57159046A JP 4378681 A JP4378681 A JP 4378681A JP 4378681 A JP4378681 A JP 4378681A JP S57159046 A JPS57159046 A JP S57159046A
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- layer
- diffusing
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Abstract
PURPOSE:To shorten the working steps and to reduce the cost of a semiconductor integrated circuit device by simultaneously forming the diffusing steps of diffusing the base of a transistor or diffusing a resistor necessary to form an IC on the same IC substrate. CONSTITUTION:A P<+> type low resistance diffused region 15 and N<+> type contacting regions 16a, 16b contacted with the region 15 are formed on the surface of an N type epitaxial layer 14 isolated by an N<+> type pressed layer 12 and a P<+> type isolation region 13 formed on a P type silicon substrate 11, and electrode windows 19a, 19b opened at the intermediate between the regions 16a, 16b and the region 15 are formed at oxidized films 17, 18 on the layer 14. Aluminum wires 21a, 21b are connected through the electrode windows and the low resistance diffused layer, and are crossed with an aluminum wire 22 formed through the insulating layers 17, 18 thereon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4378681A JPS57159046A (en) | 1981-03-25 | 1981-03-25 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4378681A JPS57159046A (en) | 1981-03-25 | 1981-03-25 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57159046A true JPS57159046A (en) | 1982-10-01 |
Family
ID=12673431
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4378681A Pending JPS57159046A (en) | 1981-03-25 | 1981-03-25 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57159046A (en) |
-
1981
- 1981-03-25 JP JP4378681A patent/JPS57159046A/en active Pending
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