JPS5749254A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5749254A
JPS5749254A JP12487780A JP12487780A JPS5749254A JP S5749254 A JPS5749254 A JP S5749254A JP 12487780 A JP12487780 A JP 12487780A JP 12487780 A JP12487780 A JP 12487780A JP S5749254 A JPS5749254 A JP S5749254A
Authority
JP
Japan
Prior art keywords
layer
hole
semiconductor device
impurity region
metallic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12487780A
Other languages
Japanese (ja)
Inventor
Kazuhito Misu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12487780A priority Critical patent/JPS5749254A/en
Publication of JPS5749254A publication Critical patent/JPS5749254A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the integration of a semiconductor device by connecting a polysilicon layer with holes to an impurity region formed in a substrate, connecting the polysilicon layer to the metallic wiring layer at the part except the hole, thereby enabling to reduce the allowance between the metallic wires. CONSTITUTION:In a contacting system for connecting metallic wires to reduce the resistance of a diffused layer on an impurity region, a polysilicon layer 316 is interposed between an impurity region 309 and a wiring layer 302. The layers 309 and 316 are contacted through the hole 307 formed at an insulating film 317, and a wire 302 and the layer 306 are contacted via a hole 308 of an insulaing film 316. The position of the hole 308 is formed on the region different from the position of the hole 307. Thus, the deterioration in the characteristics due to the displacement of the position at the time of etching can be prevented, it can eliminate the need for roundabout of the wire 302. For example, other metallic wiring layers 301, 303, or the like can be formed on the layer 306, thereby enabling to improve the integration of the semiconductor device.
JP12487780A 1980-09-09 1980-09-09 Semiconductor device Pending JPS5749254A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12487780A JPS5749254A (en) 1980-09-09 1980-09-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12487780A JPS5749254A (en) 1980-09-09 1980-09-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5749254A true JPS5749254A (en) 1982-03-23

Family

ID=14896297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12487780A Pending JPS5749254A (en) 1980-09-09 1980-09-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5749254A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6218694B1 (en) 1998-06-25 2001-04-17 Nec Corporation Semiconductor memory device and method for manufacturing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6218694B1 (en) 1998-06-25 2001-04-17 Nec Corporation Semiconductor memory device and method for manufacturing same

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