JPS5796553A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5796553A
JPS5796553A JP55173006A JP17300680A JPS5796553A JP S5796553 A JPS5796553 A JP S5796553A JP 55173006 A JP55173006 A JP 55173006A JP 17300680 A JP17300680 A JP 17300680A JP S5796553 A JPS5796553 A JP S5796553A
Authority
JP
Japan
Prior art keywords
film
layer
oxide film
electrode
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55173006A
Other languages
Japanese (ja)
Inventor
Shigeru Ozora
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55173006A priority Critical patent/JPS5796553A/en
Publication of JPS5796553A publication Critical patent/JPS5796553A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To improve reliability by a method wherein an insulation layer under a bump electrode is composed of four layers, namely a thermal oxide film, an insulating film as an impurity region protecting film, an oxide film as an interior wiring region protecting film and a nitride film which are formed on the surface of a substrate successively in respective order. CONSTITUTION:An insulating layer in which an aperture is made as a through hole to an impurity diffused region 22 in a semiconductor substrate 21 such as Si of a semiconductor device with a vamp electrode is composed of a thermal oxide film 23 and a silicone nitride film 24 as a diffused region protecting layer. The first wiring layer 25a and an insulating layer 25b are formed by a method such as selective oxidization. The third and the fourth insulating films are formed as an Si oxide film 26a and a silicone nitride film 26b respectively by a method such as CVD. A contact hole connected to the first wiring layer 25a is formed and the second wiring layer is composed of a Ti film 27, Pt film 28 and an Au film 29 and the Au vamp electrode 30 is formed. A thermal stress given to the vamp electrode 30 is absorbed by adhesion of the silicone nitride film and the four-layer insulation.
JP55173006A 1980-12-08 1980-12-08 Semiconductor device Pending JPS5796553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55173006A JPS5796553A (en) 1980-12-08 1980-12-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55173006A JPS5796553A (en) 1980-12-08 1980-12-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5796553A true JPS5796553A (en) 1982-06-15

Family

ID=15952437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55173006A Pending JPS5796553A (en) 1980-12-08 1980-12-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5796553A (en)

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