JPS56111250A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPS56111250A JPS56111250A JP1384680A JP1384680A JPS56111250A JP S56111250 A JPS56111250 A JP S56111250A JP 1384680 A JP1384680 A JP 1384680A JP 1384680 A JP1384680 A JP 1384680A JP S56111250 A JPS56111250 A JP S56111250A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- psg11
- electron beam
- melted
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 101000617707 Homo sapiens Pregnancy-specific beta-1-glycoprotein 11 Proteins 0.000 abstract 3
- 101000617728 Homo sapiens Pregnancy-specific beta-1-glycoprotein 9 Proteins 0.000 abstract 3
- 102100021983 Pregnancy-specific beta-1-glycoprotein 9 Human genes 0.000 abstract 3
- 238000010894 electron beam technology Methods 0.000 abstract 3
- 230000005855 radiation Effects 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 abstract 2
- 230000008018 melting Effects 0.000 abstract 2
- 238000002844 melting Methods 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 230000002265 prevention Effects 0.000 abstract 1
- 238000000992 sputter etching Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To obtain a multilayered wiring where no disconnection caused by a step occurs, by melting an inter-layer insulation film of a multilayered wiring on a semiconductor substrate having an active layer by means of electron beam radiation. CONSTITUTION:A field oxide film 4, a gate oxide film 5, an n type source 8, a drain 9, a pollicrystalline Si gate electrode 6, a polycrystalline Si wiring 7 are formed on a p<-> type Si substrate. A PSG11 is stacked on a CVD SiO2 film 10. The PSG11 is melted by means of electron beam radiation to ease a step between the wirings 6, 7. Then selective openings 12-14 are formed and an Al film evaporation is applied. An ion etching of CCl4 is performed to pattern the wiring 15-17. Further, an SiO2 18 and a PSG19 are stacked and subjected to electron beam radiation to smooth the surface without melting the wiring 15-17. Then selective opening 20, 21 are made to form an Al wiring 22, 23. With such an arrangement, the PSG11, 19 only are melted locally, while the Al wiring is not melted, resulting in the prevention of rediffustion of the diffusion layers 8, 9 and a device with greater intergration of high reliability.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1384680A JPS56111250A (en) | 1980-02-07 | 1980-02-07 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1384680A JPS56111250A (en) | 1980-02-07 | 1980-02-07 | Preparation of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56111250A true JPS56111250A (en) | 1981-09-02 |
Family
ID=11844633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1384680A Pending JPS56111250A (en) | 1980-02-07 | 1980-02-07 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56111250A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3228399A1 (en) * | 1982-07-29 | 1984-02-02 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING A MONOLITHICALLY INTEGRATED CIRCUIT |
| EP0202572A2 (en) * | 1985-05-13 | 1986-11-26 | Nippon Telegraph And Telephone Corporation | Method for forming a planarized aluminium thin film |
| JPS62281350A (en) * | 1986-05-29 | 1987-12-07 | Toshiba Corp | Semiconductor device and manufacture thereof |
-
1980
- 1980-02-07 JP JP1384680A patent/JPS56111250A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3228399A1 (en) * | 1982-07-29 | 1984-02-02 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING A MONOLITHICALLY INTEGRATED CIRCUIT |
| EP0202572A2 (en) * | 1985-05-13 | 1986-11-26 | Nippon Telegraph And Telephone Corporation | Method for forming a planarized aluminium thin film |
| JPS62281350A (en) * | 1986-05-29 | 1987-12-07 | Toshiba Corp | Semiconductor device and manufacture thereof |
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