JPH01244659A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01244659A JPH01244659A JP63072276A JP7227688A JPH01244659A JP H01244659 A JPH01244659 A JP H01244659A JP 63072276 A JP63072276 A JP 63072276A JP 7227688 A JP7227688 A JP 7227688A JP H01244659 A JPH01244659 A JP H01244659A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- layer
- silicon oxide
- silicon layer
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 5
- 239000013078 crystal Substances 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- -1 phosphorus ions Chemical class 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 210000004709 eyebrow Anatomy 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に抵抗負荷型スタティッ
クＲＡＭを有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a resistive load type static RAM.
抵抗負荷型のＭＯＳスタティックＲＡＭは高集積化、高
速化に適しており、負荷素子として多結晶シリコン層が
一般的に用いられている。多結晶シリコン層は、化学気
相成長法（以下ＣＶＤ法と記す）により容易に形成され
、膜厚均一性及びその再現性、パターン上の被覆性等に
優れている他、加工性も良く、また、膜厚を薄くするこ
とで高抵抗が容易に得られるという利点がある。A resistive load type MOS static RAM is suitable for high integration and high speed, and a polycrystalline silicon layer is generally used as a load element. Polycrystalline silicon layers are easily formed by chemical vapor deposition (hereinafter referred to as CVD), and have excellent film thickness uniformity, reproducibility, pattern coverage, etc., as well as good processability. Another advantage is that high resistance can be easily obtained by reducing the film thickness.
第３図（ａ）〜（ｃ）は従来の半導体装置の製造方法を
説明するための工程順に示した半導体チップの断面図で
ある。FIGS. 3(a) to 3(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a semiconductor device.
第３図（ａ）に示すように、シリコン基板１の上に１．
０μｍの素子分離用のフィールド絶縁膜２を選択的に設
けて素子形成領域を区画し、熱酸化法により前記素子形
成領域の表面を酸化してゲート絶縁膜３を設ける０次に
、ゲート絶縁膜３を含む表面にＣＶＤ法により５ Ｘ
１０ ”Ｃ１１−’程度のリンをドープした多結晶シリ
コン層を０．４μｍの厚さに堆積し、ホトリソグラフィ
技術及びＲｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ
（以下ＲＩＥと記す）により前記多結晶シリコン層を選
択的にエツチングしてゲート電極４を形成する０次に、
ゲート電極４を含む表面にＣＶＤ法によりＰＳＧｆｆ５
を０．４μｍの厚さに堆積させた後、これを選択的にエ
ツチングしてゲート電極４のコンタクト孔を設ける。As shown in FIG. 3(a), 1.
A field insulating film 2 of 0 μm for element isolation is selectively provided to demarcate an element formation region, and the surface of the element formation region is oxidized by a thermal oxidation method to form a gate insulating film 3. Next, a gate insulating film 3 is formed. 5X by CVD method on the surface containing 3
10 A phosphorus-doped polycrystalline silicon layer of about 10"C11-' was deposited to a thickness of 0.4 μm, and photolithography technology and reactive ion etching were performed.
The polycrystalline silicon layer is selectively etched by RIE (hereinafter referred to as RIE) to form the gate electrode 4.
PSGff5 is deposited on the surface including the gate electrode 4 by CVD method.
is deposited to a thickness of 0.4 μm, and then selectively etched to form a contact hole for the gate electrode 4.
次に、第３図（ｂ）に示すように、前記コンタクト孔を
含む表面にＣＶＤ法により多結晶シリコン層１６を０．
１μｍの厚さに堆積し、これを選択的にエツチングして
ゲート電極４と電気的に接続し、且つ、ＰＳＧ膜５の上
に延在する抵抗層を形成する。Next, as shown in FIG. 3(b), a polycrystalline silicon layer 16 is formed on the surface including the contact hole by a CVD method.
It is deposited to a thickness of 1 μm and selectively etched to form a resistive layer electrically connected to the gate electrode 4 and extending over the PSG film 5.
次に、第３図（ｃ）に示すように、多結晶シリコン層１
６を含む表面にＣＶＤ法により窒化シリコン膜９を０．
１μｍの厚さに堆積させた後、配線形成領域上の窒化シ
リコン膜９を選択的に除去する０次に、窒化シリコン膜
９をマスクとしてリンイオンを加速エネルギー６０ｋｅ
Ｖ、ドーズ量２ Ｘ １０１６ｃｍ−２でイオン注入し
、前記抵抗層と接続する配線層１１を形成する０次に、
ＣＶＤ法でＰＳＧ膜１０を０．５μｍの厚さに堆積し、
これを選択的にエツチングして配線層１１のコンタクト
孔を設け、前記コンタクト孔の配線層１１と電気的に接
続するアルミニウム配線１２を選択的に形成する。Next, as shown in FIG. 3(c), a polycrystalline silicon layer 1
A silicon nitride film 9 is deposited on the surface including 6 by CVD method.
After depositing to a thickness of 1 μm, the silicon nitride film 9 on the wiring formation area is selectively removed.Next, phosphorus ions are accelerated using the silicon nitride film 9 as a mask at an energy of 60ke.
ion implantation at a dose of 2 x 1016 cm-2 to form a wiring layer 11 connected to the resistance layer.
A PSG film 10 was deposited to a thickness of 0.5 μm using the CVD method,
This is selectively etched to form a contact hole in the wiring layer 11, and an aluminum wiring 12 electrically connected to the wiring layer 11 in the contact hole is selectively formed.
上述した従来の半導体装置は、多結晶シリコン層で構成
される抵抗層が６００℃程度の温度で堆積された後、拡
散層形成時の熱処理、眉間絶縁膜のりフロー時の熱処理
等の９００℃を超える高温の熱処理を受けることによっ
て、多結晶シリコン層の結晶ダレインが成長して抵抗値
が低下するため、所望の抵抗値を維持できないという問
題点がある。この為、ＩＭビット以上の大容量ＳＲＡＭ
で必要とされる高抵抗（数ＴΩ）の負荷素子を、従来の
多結晶シリコン層では実現できなかった。In the conventional semiconductor device described above, after a resistive layer made of a polycrystalline silicon layer is deposited at a temperature of about 600°C, heat treatment at 900°C is performed, such as heat treatment during formation of a diffusion layer and heat treatment during flow of an insulating film between the eyebrows. There is a problem in that a desired resistance value cannot be maintained because the crystal dalein of the polycrystalline silicon layer grows and the resistance value decreases due to heat treatment at an exceedingly high temperature. For this reason, large capacity SRAM with more than IM bit
A load element with high resistance (several TΩ) required for this could not be realized using conventional polycrystalline silicon layers.
本発明の目的は、高温処理を行っても抵抗値が変化しな
い負荷素子を有する高信頼性の半導体装置を提供するこ
とにある。An object of the present invention is to provide a highly reliable semiconductor device having a load element whose resistance value does not change even when subjected to high temperature processing.
本発明の半導体装置は、半導体基板に設けた半導体素子
に接続して設けた抵抗素子を有する半導体装置において
、前記抵抗素子が多結晶シリコン層と少くとも一層の酸
化シリコン層とを交互に積層して設けた多層構造を有し
ている。A semiconductor device of the present invention includes a resistor element connected to a semiconductor element provided on a semiconductor substrate, wherein the resistor element is formed by alternately laminating polycrystalline silicon layers and at least one silicon oxide layer. It has a multi-layered structure.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の製造方法を説明するた
めの工程順に示した半導体チップの断面図である。FIG. 1 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a manufacturing method according to a first embodiment of the present invention.
まず、第１図（ａ）に示すように、シリコン基板１の上
に素子分離用のフィールド絶縁膜２を選択的に形成して
素子形成領域を区画する０次に、熱酸化法により前記素
子形成領域の表面にゲート絶縁膜３を設ける６次に、ゲ
ート絶縁膜３を含む表面にＣＶＤ法により５ Ｘ １０
”Ｃ１１−’程度のリンをドープした多結晶シリコン
層を０．４μｍの厚さに堆積し、これをホトリソグラフ
ィー技術及びＲＩＥによって選択的にエツチングしてゲ
ート電極４を形成する０次に、ゲート電極４を含む表面
にＣＶＤ法によりＰＳＧ膜５を０．４μｍの厚さに堆積
した後、ゲート電極４Ｑコンタクト孔を設ける０次に、
前記コンタクト孔を含む表面にＣＶＤ法により多結晶シ
リコン層６を７０ｎｍの厚さに堆積し、６００℃の乾燥
酸素雰囲気中で多結晶シリコン層６の表面に２〜１０ｎ
ｍの厚さの酸化シリコン層７を形成する。更に酸化シリ
コン層７の上にＣＶＤ法により多結晶シリコン層８を７
０ｎｍの厚さに堆積する。First, as shown in FIG. 1(a), a field insulating film 2 for element isolation is selectively formed on a silicon substrate 1 to demarcate an element formation region. A gate insulating film 3 is provided on the surface of the formation region.Next, the surface including the gate insulating film 3 is coated with a 5×10
A polycrystalline silicon layer doped with phosphorus of approximately "C11-" is deposited to a thickness of 0.4 μm, and this is selectively etched by photolithography and RIE to form the gate electrode 4. After depositing a PSG film 5 to a thickness of 0.4 μm on the surface including the electrode 4 by the CVD method, a contact hole for the gate electrode 4Q is formed.
A polycrystalline silicon layer 6 is deposited to a thickness of 70 nm on the surface including the contact hole by the CVD method, and 2 to 10 nm thick is deposited on the surface of the polycrystalline silicon layer 6 in a dry oxygen atmosphere at 600°C.
A silicon oxide layer 7 having a thickness of m is formed. Further, a polycrystalline silicon layer 8 is formed on the silicon oxide layer 7 by the CVD method.
Deposit to a thickness of 0 nm.
次に、第１図（ｂ）に示すように、多結晶シリコン層８
と酸化シリコン層７及び多結晶シリコン層６を順次選択
的にエツチングして前記コンタクト孔のゲート電極４と
接続する抵抗素子を形成する。ここで、酸化シリコン層
７が存在するために後工程の熱処理によって多結晶シリ
コン層６．８の結晶ダレインが成長するのを抑制して抵
抗値の変化を押えることができる。また、乾燥酸素雰囲
気中で多結晶シリコン層６の表面に設けた薄い酸化シリ
コン層７はウィークスポット（ｗｅａｋ ５ｐｏｔ）が
多く、電界強度との関係もあり、絶縁膜としての働きは
無視できる状態にあることが、昭和５９年応用物理学会
秋季大会予稿集１４ａ−Ｂ−８及び１４ａ−Ｂ−９にも
紹介されているように、知られている。Next, as shown in FIG. 1(b), a polycrystalline silicon layer 8
Then, the silicon oxide layer 7 and the polycrystalline silicon layer 6 are selectively etched in order to form a resistance element connected to the gate electrode 4 of the contact hole. Here, due to the presence of the silicon oxide layer 7, it is possible to suppress the growth of the crystalline drain of the polycrystalline silicon layer 6.8 by heat treatment in a subsequent step, thereby suppressing the change in resistance value. In addition, the thin silicon oxide layer 7 provided on the surface of the polycrystalline silicon layer 6 in a dry oxygen atmosphere has many weak spots (weak spots), which is also related to the electric field strength, and its function as an insulating film can be ignored. One thing is known, as introduced in the 1981 Japan Society of Applied Physics Autumn Conference Proceedings 14a-B-8 and 14a-B-9.
次に、第１図（ｃ）に示すように、前記抵抗素子を含む
表面にＣＶＤ法により窒化シリコン膜９を０．１μｍの
厚さに堆積し、選択的にエツチングして前記抵抗素子の
配線形成領域を含む部分を露出させる。次に、窒化シリ
コン膜９をマスクとして前記配線形成領域にリンイオン
を加速エネルギー６０ｋｅＶ、ドーズ量Ｉ Ｘ １０１
６Ｃ１１−”の条件でイオン注入して配線層１１を形成
する０次に、ＣＶＤ法によりＰＳＧ膜１０を０．５μｍ
の厚さに堆積し、選択的にエツチングして配線層１１の
コンタクト孔を形成する０次に前記コンタクト孔を含む
表面にアルミニウム層を堆積し、これを選択的にエツチ
ングして配線層１１とコンタクトするアルミニウム配線
１２を形成する。Next, as shown in FIG. 1(c), a silicon nitride film 9 is deposited to a thickness of 0.1 μm on the surface including the resistor element by CVD, and selectively etched to form the wiring of the resistor element. Expose the portion including the formation area. Next, using the silicon nitride film 9 as a mask, phosphorus ions are accelerated into the wiring formation region at an energy of 60 keV and a dose of I x 101.
The wiring layer 11 is formed by ion implantation under the conditions of 6C11-'', and then the PSG film 10 is deposited to a thickness of 0.5 μm using the CVD method.
Then, an aluminum layer is deposited on the surface including the contact hole and selectively etched to form a contact hole in the wiring layer 11. An aluminum wiring 12 for contact is formed.
第２図（ａ）〜（Ｃ）は本発明の第２の実施例の製造方
法を説明するための工程順に示した半導体チップの断面
図である。FIGS. 2(a) to 2(C) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the second embodiment of the present invention.
第２図＜ａ）に示すように、第１図（ａ）の多結晶シリ
コン層８を形成するまでの工程を第１の実施例と全く同
じ工程で形成した後、６００℃の乾燥雰囲気中で多結晶
シリコン層８の表面に２〜１０ｎｍの厚さの酸化シリコ
ンＭ１３を形成し、酸化シリコン膜１３の上にＣＶＤ法
により多結晶シリコン層１４を０．１２μｍの厚さに堆
積する０次に、ホトリソグラフィ技術及びＲＩＥ法によ
り多結晶シリコン層１４、酸化シリコン層１３、多結晶
シリコン層８、酸化シリコンＩＩ７、多結晶シリコン層
６を選択的に順次エツチングして多結晶シリコン層及び
酸化シリコン層を交互に積層した多層構造の抵抗素子を
形成する。As shown in FIG. 2<a), after forming the polycrystalline silicon layer 8 in FIG. 1(a) in exactly the same steps as in the first embodiment, A silicon oxide M13 having a thickness of 2 to 10 nm is formed on the surface of the polycrystalline silicon layer 8, and a polycrystalline silicon layer 14 is deposited to a thickness of 0.12 μm on the silicon oxide film 13 by the CVD method. Then, the polycrystalline silicon layer 14, the silicon oxide layer 13, the polycrystalline silicon layer 8, the silicon oxide II 7, and the polycrystalline silicon layer 6 are selectively and sequentially etched using photolithography technology and RIE method to form the polycrystalline silicon layer and the silicon oxide layer. A resistor element having a multilayer structure in which layers are alternately laminated is formed.
次に、第２図（ｂ）に示すように、全面にホトレジスト
膜１５を形成してバターニングし、前記抵抗素子の配線
形成領域を覆うパターンを形成する。Next, as shown in FIG. 2(b), a photoresist film 15 is formed on the entire surface and patterned to form a pattern covering the wiring formation area of the resistor element.
次に、第２図（Ｃ）に示すように、ホトレジスト膜１５
をマスクとして多結晶シリコンＮ１４をＲＩＥ法により
エツチングし、配線形成領域のみに多結晶シリコン層１
４を残す、このとき酸化シリコン層１３がエツチングス
トッパとなり制御よく多結晶シリコン層１４のみを除去
でき、高抵抗領域として残すべき部分は薄く、低抵抗の
配線領域となるべき部分は厚い多結晶シリコン層１４が
形成される。次に、リンイオンを加速エネルギー１６０
ｋｅＶ、ドーズ量２ Ｘ １０１６Ｃ１１−”の条件で
イオン注入する。このとき、高加速エネルギーにより前
記抵抗素子の薄い領域はイオンが突抜けるためドープさ
れず、厚い領域のみドープされて配線層１１が形成され
る。以後、眉間絶縁膜としてのＰＳＧＪｌｉを形成し、
コンタクト孔を設け、アルミニウム配線を形成する工程
を第１の実施例と同様に行い半導体装置を得る。Next, as shown in FIG. 2(C), the photoresist film 15
Using this as a mask, polycrystalline silicon N14 is etched by the RIE method to form a polycrystalline silicon layer 1 only in the wiring formation region.
At this time, the silicon oxide layer 13 acts as an etching stopper and only the polycrystalline silicon layer 14 can be removed with good control.The part that should be left as a high-resistance region is thin, and the part that should be a low-resistance wiring region is made of thick polycrystalline silicon. Layer 14 is formed. Next, accelerate the phosphorus ions with an energy of 160
keV and a dose of 2 x 1016C11-''. At this time, the thin region of the resistor element is not doped because the ions penetrate through the high acceleration energy, and only the thick region is doped to form the wiring layer 11. After that, PSGJli is formed as an insulating film between the eyebrows,
A semiconductor device is obtained by forming contact holes and forming aluminum wiring in the same manner as in the first embodiment.
以上説明したように本発明は、抵抗素子として多結晶シ
リコン層と薄い酸化シリコン膜を交互に積層した多層構
造にしたことにより、抵抗素子形成後の高温熱処理工程
（９００℃程度）を経た後も、多結晶シリコン層のシリ
コン原子の移動がシリコン酸化膜によって阻止されるた
め、結晶のグレイン成長を抑制し、抵抗素子の抵抗値を
変化させることが無く半導体装置の信頼性を向上させる
という効果を有する。As explained above, the present invention has a multilayer structure in which polycrystalline silicon layers and thin silicon oxide films are alternately laminated as a resistance element, so that even after a high temperature heat treatment process (approximately 900°C) after the formation of the resistance element, Since the movement of silicon atoms in the polycrystalline silicon layer is blocked by the silicon oxide film, crystal grain growth is suppressed, and the reliability of semiconductor devices is improved without changing the resistance value of the resistor element. have
第１図（ａ）〜（ｃ）及び第２図（ａ）〜（Ｃ）は本発
明の第１及び第２の実施例の製造方法を説明するための
工程順に示した半導体チップの断面図、第３図（ａ）〜
（Ｃ）は従来の半導体装置の製造方法を説明するための
工程順に示した半導体チップの断面図である。
１・・・シリコン基板、２・・・フィールド絶縁膜、３
・・・ゲート絶縁膜、４・・・ゲート電極、５・・・Ｐ
ＳＧ膜、６・・・多結晶シリコン層、７・・・酸化シリ
コン層、８・・・多結晶シリコン層、９・・・窒化シリ
コン膜、１０・・・ＰＳＧ膜、１１・・・配線層、１２
・・・アルミニウム配線、１３・・・酸化シリコン層、
１４・・・多結晶シリコン層、１５・・・ホトレジスト
膜、１６・・・多結晶シリコン層。1(a)-(c) and FIG. 2(a)-(C) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the first and second embodiments of the present invention. , Figure 3(a)~
(C) is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a semiconductor device. 1... Silicon substrate, 2... Field insulating film, 3
...Gate insulating film, 4...Gate electrode, 5...P
SG film, 6... Polycrystalline silicon layer, 7... Silicon oxide layer, 8... Polycrystalline silicon layer, 9... Silicon nitride film, 10... PSG film, 11... Wiring layer , 12
...Aluminum wiring, 13...Silicon oxide layer,
14... Polycrystalline silicon layer, 15... Photoresist film, 16... Polycrystalline silicon layer.
Claims (1)
子を有する半導体装置において、前記抵抗素子が多結晶
シリコン層と少くとも一層の酸化シリコン層とを交互に
積層して設けた多層構造を有することを特徴とする半導
体装置。In a semiconductor device having a resistive element connected to a semiconductor element provided on a semiconductor substrate, the resistive element has a multilayer structure in which polycrystalline silicon layers and at least one silicon oxide layer are alternately laminated. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63072276A JPH01244659A (en) | 1988-03-25 | 1988-03-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63072276A JPH01244659A (en) | 1988-03-25 | 1988-03-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01244659A true JPH01244659A (en) | 1989-09-29 |
Family
ID=13484601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63072276A Pending JPH01244659A (en) | 1988-03-25 | 1988-03-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01244659A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08125022A (en) * | 1994-10-28 | 1996-05-17 | Nec Corp | Manufacture of semiconductor device |
| US6287915B1 (en) | 1997-11-19 | 2001-09-11 | Nec Corporation | Semiconductor device and manufacturing method therefor |
-
1988
- 1988-03-25 JP JP63072276A patent/JPH01244659A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08125022A (en) * | 1994-10-28 | 1996-05-17 | Nec Corp | Manufacture of semiconductor device |
| US6287915B1 (en) | 1997-11-19 | 2001-09-11 | Nec Corporation | Semiconductor device and manufacturing method therefor |
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