JPS59214265A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59214265A JPS59214265A JP8857483A JP8857483A JPS59214265A JP S59214265 A JPS59214265 A JP S59214265A JP 8857483 A JP8857483 A JP 8857483A JP 8857483 A JP8857483 A JP 8857483A JP S59214265 A JPS59214265 A JP S59214265A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- electrode
- dirt
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000007772 electrode material Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 239000012298 atmosphere Substances 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 4
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 239000012535 impurity Substances 0.000 claims abstract 4
- 238000000151 deposition Methods 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims 1
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 7
- 230000014759 maintenance of location Effects 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関し、特にＰＲＯＭ（
Ｐｒｏｇｒａｍａｂｌｅ Ｒｅａｄ ０ｎｌｙ Ｍｅｍ
ｏｒｙ）のような記憶機能を有する半導体装置の製造方
法に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device (PROM).
Programmable Read Only Mem
The present invention relates to a method of manufacturing a semiconductor device having a memory function such as (ory).
従来、 ＦＲＯＭは第１図（ａ）及び（ｂ）に示すよう
な方法により製造されている。Conventionally, FROM has been manufactured by the method shown in FIGS. 1(a) and 1(b).
まず、例えばＰ型シリコン基板Ｉ表面に通常の選択酸化
法により素子分離膜２を形成し、第１の熱酸化膜、第１
の多結晶シリコン膜、第２の熱酸化膜及び第２の多結晶
シリコン膜を順次積層した後、これらを順次・母ターニ
ングしてコントロールゲート電極３．第１ダート酸化膜
４゜フローティングゲート電極５及び第２ダート酸化膜
６からなる積層構造を形成する。この際、第２ダート酸
化膜４及び第１ダート酸化膜６はオーバーエッチングサ
してコントロールゲート電極３及びフローティングダー
ト電極５よりも寸法が小さくなっている。First, for example, an element isolation film 2 is formed on the surface of a P-type silicon substrate I by a normal selective oxidation method, and a first thermal oxide film, a first
After sequentially stacking the polycrystalline silicon film, the second thermal oxide film, and the second polycrystalline silicon film, these are sequentially turned to form the control gate electrode 3. A laminated structure consisting of a first dirt oxide film 4° floating gate electrode 5 and a second dirt oxide film 6 is formed. At this time, the second dirt oxide film 4 and the first dirt oxide film 6 are over-etched and have smaller dimensions than the control gate electrode 3 and the floating dirt electrode 5.
次に、前記コントロールゲ−ト電極３をマスクとして利
用し、例えば７５Ａ、＋−ｑイオン注入した後、熱処理
してＮ型ソース領域７及びＮ＋ｆｊ１ドレイン領域８を
形成する（第１図（ａ）図示）。次いで、気相成長法に
より層間絶縁膜９を堆積する（同図（ｂ）図示）。以下
、通常の工程に従い、コンタクトホールを開孔し、更に
ＡＡ膜を蒸着した後、・母ターニングしてＡｔ配線を形
成し、ＦＲＯＭを製造する。Next, using the control gate electrode 3 as a mask, for example, 75A, +-q ions are implanted, followed by heat treatment to form an N-type source region 7 and an N+fj1 drain region 8 (see FIG. 1(a)). (Illustrated). Next, an interlayer insulating film 9 is deposited by a vapor phase growth method (as shown in FIG. 3(b)). Thereafter, according to the usual steps, a contact hole is opened, an AA film is further deposited, and then an At wiring is formed by main turning, thereby manufacturing a FROM.
なお、層間絶縁膜９を堆積する前に熱酸化を行ない、コ
ントロールゲート電極３．フローティングダート電極５
及び基板１表面に熱酸化膜を形成する場合もある。Note that before depositing the interlayer insulating film 9, thermal oxidation is performed to form the control gate electrode 3. floating dart electrode 5
A thermal oxide film may also be formed on the surface of the substrate 1.
上述した従来の方法を用いた場合、第１図（ｂ）中Ｘ部
分を拡大して示す第２図中の斜線部分、すなわちフロー
ティングゲート電極５のドレイン領域８側の端部近傍に
気相成長により形成される層間絶縁膜９は分子の密度が
粗く、電気的絶縁性が劣っている。このため、フローテ
ィングゲト電極５内に蓄えられた電荷がドレイン領域８
側へ流出し易くなり、記憶保持という観点から信頼性上
好ましくない。When the conventional method described above is used, the vapor phase growth occurs in the shaded area in FIG. 2, which is an enlarged view of the X portion in FIG. The interlayer insulating film 9 formed by the above method has a coarse molecular density and poor electrical insulation. Therefore, the charges stored in the floating gate electrode 5 are transferred to the drain region 8.
This tends to leak to the side, which is unfavorable from the viewpoint of memory retention and reliability.
また、第３図に示すように層間絶縁膜９を堆積する前（
（熱酸化を行なってフローティングダート電極５の露出
面上及びドレイン領域８表面上に熱酸化膜ｒｏｆ形成し
たとしても、やはり同図中の斜線部分の層間絶縁膜９の
膜質は悪く、電荷保持特性は若−干しか改善されない。Furthermore, as shown in FIG. 3, before depositing the interlayer insulating film 9 (
(Even if thermal oxidation is performed to form a thermal oxide film rof on the exposed surface of the floating dirt electrode 5 and the surface of the drain region 8, the film quality of the interlayer insulating film 9 in the shaded area in the figure is still poor, and the charge retention property is is only slightly improved.
本発明は上記事情に鑑みてなされたものであり、フロー
ティングゲート電極のドレイン側の端部近傍に形成され
る絶縁膜の膜質を改善することにより電荷の保持特性の
良好な半導体装置を製造し得る方法を提供しようとする
ものである。The present invention has been made in view of the above circumstances, and it is possible to manufacture a semiconductor device with good charge retention characteristics by improving the quality of the insulating film formed near the end of the floating gate electrode on the drain side. It is intended to provide a method.
本発明の半導体装置の製造方法は、まず半導体基板の素
子領域上に第１の絶縁膜、第１のダート電極材料膜、第
２の絶縁膜及び第２のダート電極材料膜を積層し、・ぐ
ターニングして第２のゲート電極（コントロールゲート
電極）、第２のダート絶縁膜及び第１のダート電極（フ
ローティングゲート電極）を形成した後、第１の絶縁膜
はそのままの状態で第２のゲート電極。The method for manufacturing a semiconductor device of the present invention includes first stacking a first insulating film, a first dirt electrode material film, a second insulating film, and a second dirt electrode material film on an element region of a semiconductor substrate; After forming a second gate electrode (control gate electrode), a second dirt insulating film, and a first dirt electrode (floating gate electrode) by turning the first insulating film as it is, a second gate electrode is formed. gate electrode.
第２のダート絶縁膜及び第１のダート電極の側面にのみ
絶縁性被膜（例えばＣＶＤ酸化膜）を残存させ、次に露
出した第１の絶縁膜をエツチングして第１のゲート絶縁
膜を形成した後、ソース、ドレイン領域形成のためのイ
オン注入を行ない、更に酸化または窒素雰囲気中で熱処
理してソース、ドレイン領域を形成することを特徴とす
るものである。An insulating film (e.g., CVD oxide film) is left only on the side surfaces of the second dirt insulating film and the first dirt electrode, and then the exposed first insulating film is etched to form a first gate insulating film. After that, ion implantation is performed to form the source and drain regions, and further heat treatment is performed in an oxidation or nitrogen atmosphere to form the source and drain regions.
こうした方法によれば、第１のダート電極（フローティ
ング電極）のドレイン領域側の端部近傍に存在する絶縁
膜は第１のダート絶縁膜、及び側面に残存した絶縁性被
膜と第１のダート電極との間で成長した熱酸化膜である
ので膜質が良好であり、電荷の保持特性を改善すること
ができる。According to this method, the insulating film existing near the end of the first dirt electrode (floating electrode) on the drain region side is the first dirt insulating film, and the insulating film remaining on the side surface and the first dirt electrode Since it is a thermally oxidized film grown between the two, the film quality is good and the charge retention characteristics can be improved.
以下、本発明の実施例を第４図（ａ）〜（ｆ） ｋ参照
して説明する。Hereinafter, embodiments of the present invention will be described with reference to FIGS. 4(a) to (f)k.
まず、Ｐ型シリコン基板２１表面に通常の選択酸化法に
より素子分離膜２２を形成した後、素子分離膜２２によ
り囲まれた素子領域表面に第１の熱酸化膜２３を形成す
る。次に、この第１の熱酸化膜２３上に第１の多結晶シ
ｌＪコン膜２４、第２の熱酸化膜２５及び第２の多結晶
シリコン膜２６を順次積層する（第４図（−）図示）。First, an element isolation film 22 is formed on the surface of a P-type silicon substrate 21 by a normal selective oxidation method, and then a first thermal oxide film 23 is formed on the surface of an element region surrounded by the element isolation film 22. Next, on this first thermal oxide film 23, a first polycrystalline silicon film 24, a second thermal oxide film 25, and a second polycrystalline silicon film 26 are sequentially laminated (see FIG. ).
つづいて、第２の多結晶シリコン膜２６上に図示しない
ホトレジストパターンを形成した後、異方性エツチング
により第２の多結晶シリコン膜２６．第２の熱酸化膜２
５及び第１の多結晶シリコン膜２４を順次ｉ４ターニン
グしてコントロールダート電極２７．第２のダート酸化
膜２８及びフローティングゲート電極２９を形成する（
同図（ｂ）図示）。Subsequently, a photoresist pattern (not shown) is formed on the second polycrystalline silicon film 26, and then the second polycrystalline silicon film 26. Second thermal oxide film 2
5 and the first polycrystalline silicon film 24 are sequentially i4 turned to form a control dirt electrode 27. Forming a second dirt oxide film 28 and floating gate electrode 29 (
Figure (b) shown).
次いで、第１の熱酸化膜２３はそのままの状態で全面に
例えば２０００ＸのＣＶＤ酸化膜を堆積した後、異方性
エツチングによりこのＣＶＤ酸化膜をその膜厚分エツチ
ングすることによりコントロールダート電極２７．第２
のダート酸化膜２Ｂ及びフローティングゲート電極２９
の側面にのみ残存ＣＶＤ酸化膜３０．３０ｆ形成する（
同図（ｃ）図示）。つづいて、再び異方性エツチングに
より露出した第１の熱酸化膜２３をエツチングして第１
のグー１−酸化膜３Ｉを形成する。Next, a CVD oxide film of, for example, 2000X is deposited on the entire surface of the first thermal oxide film 23 as it is, and then this CVD oxide film is etched to the same thickness by anisotropic etching to form the control dirt electrode 27. Second
dirt oxide film 2B and floating gate electrode 29
A remaining CVD oxide film 30.30f is formed only on the side surfaces of (
Figure (c) shown). Subsequently, the first thermal oxide film 23 exposed by anisotropic etching is etched again.
A goo 1-oxide film 3I is formed.
この際、前記残存ＣＶＤ酸化膜３０＋ｇｏもその上端か
ら第１の熱酸化膜２３の膜厚分程度エツチングされる。At this time, the remaining CVD oxide film 30+go is also etched from its upper end by about the thickness of the first thermal oxide film 23.
つづいて、コントロールゲート電極２７及び残存ＣＶＤ
酸化膜３０．３０をマスクとして利用し、例えば７５Ａ
ｓ＋全イオン注入する（同図（ｄ）図示）。Next, control gate electrode 27 and remaining CVD
Using the oxide film 30.30 as a mask, for example, 75A
All s+ ions are implanted (as shown in the same figure (d)).
次いで、１０００℃の酸化雰囲気中で熱処理を行ない、
前記砒素イオン注入層を活性化してＮ＋型ソース領域３
２及びＮ＋型ドレイン領域３３を形成する。この際、露
出した基板２１表面及びコントロールダート電極２７の
露出面には熱酸化膜３４が形成され、またコントロール
ダート電極２７及びフローティングゲート電極２９の残
存ＣＶＤ酸化膜３θ、３θによって覆われた部分でもそ
の表面に熱酸化膜が成長する（同図（ｅ）図示）。つづ
いて、全面に層間絶縁膜としてＰＳＧ膜３５を堆積した
後、コンタクトボール３６ 、、？ ６全開孔する。更
に、全面Ｋ Ａｔ膜を蒸着した後、パターニングしてＡ
ｔ配線：ｔ ｙ 、 、９７を形成し、ＦＲＯＭ半導体
装置を製造する（同図（ｆ）図示）。Next, heat treatment is performed in an oxidizing atmosphere at 1000°C,
The arsenic ion implantation layer is activated to form an N+ type source region 3.
2 and an N+ type drain region 33 are formed. At this time, a thermal oxide film 34 is formed on the exposed surface of the substrate 21 and the exposed surface of the control dirt electrode 27, and also on the portions covered by the remaining CVD oxide films 3θ, 3θ of the control dirt electrode 27 and floating gate electrode 29. A thermal oxide film grows on the surface (as shown in FIG. 2(e)). Subsequently, after depositing a PSG film 35 as an interlayer insulating film on the entire surface, contact balls 36,...? 6. Open the entire hole. Furthermore, after depositing a K At film on the entire surface, it is patterned to form an A
A t-wiring: ty, , 97 is formed to manufacture a FROM semiconductor device (as shown in FIG. 2(f)).
しかして、本発明方法によれば第４図（ｃ）図示の工程
で第１の熱酸化膜２３はそのままの状態でフローティン
グゲ−ト電極２９の側面に残存ＣＶＤ酸化膜３ｏを形成
し、同図（ｄ）図示の工程で化雰囲気中で熱処理全行な
うので、第５図に示す如くフローティングダート電極２
９の端部とドレイン領域３３との間には電気的絶縁性の
最も優れた単結晶シリコンの酸化膜である第１のゲート
酸化膜３Ｉが、フローティングゲート電極２９の側面に
は多結晶シリコンの熱酸化膜３８と緻密化さ−れたＣＶ
Ｄ酸化膜３０′がそれぞれ存在する。この後、層間絶縁
膜であるＰＳＧ膜３５を堆積すると、膜質の劣る部分（
第５図中の斜線部）はフローティングゲート電極２９の
端部からはかなり離れた位置に形成される。すなわぢ、
フローティングゲ−ト電極２９のドレイン領域３３側の
端部近傍には膜質の良好な絶縁膜だけが存在する。この
結果、第４図（ｆ）図示（７） ＰＲＯＭ 半導体装置
ではフローティングク゛−ト２９内に蓄積された電荷の
保持特性は従来の方法により得られたものと比較して２
倍以上向上することができた。According to the method of the present invention, in the step shown in FIG. 4(c), a residual CVD oxide film 3o is formed on the side surface of the floating gate electrode 29 while the first thermal oxide film 23 remains as it is. (d) In the illustrated step, the entire heat treatment is performed in a chemical atmosphere, so the floating dirt electrode 2 is formed as shown in FIG.
A first gate oxide film 3I, which is a monocrystalline silicon oxide film with the best electrical insulation, is formed between the end of the floating gate electrode 29 and the drain region 33, and a polycrystalline silicon oxide film 3I is formed on the side surfaces of the floating gate electrode 29. Thermal oxide film 38 and densified CV
A D oxide film 30' is present in each case. After that, when the PSG film 35, which is an interlayer insulating film, is deposited, the parts with poor film quality (
The shaded area in FIG. 5) is formed at a position quite far from the end of the floating gate electrode 29. Sunawaji,
Only an insulating film of good quality exists near the end of the floating gate electrode 29 on the drain region 33 side. As a result, in the PROM semiconductor device shown in (7) in FIG.
I was able to improve by more than double.
以上詳述した如く、本発明の半導体装置の製造方法によ
れば、フローティングダート電極内に蓄積された電荷の
保持特性を大幅に向上できるという顕著な効果を奏する
ものである。As described in detail above, the method for manufacturing a semiconductor device of the present invention has the remarkable effect of greatly improving the retention characteristics of the charges accumulated in the floating dart electrode.
第１図（、）及び（ｂ）は従来のＦＲＯＭ半導体装置の
製造方法を示す断面図、第２図及び第３図は第１図（ｂ
）のＸ部分の状態全拡大して示す説明図、第４図（ａ）
〜（ｆ）は本発明の実施例におけるＦＲＯＭ半導体装置
の製造方法を示す断面図、第５図は同半導体装置の一部
の状態を拡大Ｌ７て示す説明図である。
２１・・・Ｐ型シリコン基板、２２・・・素子分離膜。
２３・・・第１の熱酸化膜、２４・・・第１の多結晶シ
リコン膜、２５・・・第２の熱酸化膜、２６・・・第２
の多結晶シリコン膜、２７・・・コントロールゲート電
極、２８・・・第２のゲート酸化膜、２９・・・フロー
ティングダート電極、３ｏ・・・残存ＣＶＤ酸化膜、３
０′・・・緻密化されたＣＶＤ酸化膜、３１・・・第１
のダート酸化膜、３２・・・Ｎ＋型ソース領域、３３・
・・Ｎ＋型ドレイン領域、３４．３８・・・熱酸化膜、
３５・・・ＰＳＧ膜、３６・・・コンタクトホール、３
７・・・Ａｔ配線。
第１図
第２図 第３図
第４図FIGS. 1(a) and (b) are cross-sectional views showing a conventional FROM semiconductor device manufacturing method, and FIGS.
) Explanatory diagram showing the state of the X part in full enlargement, Figure 4 (a)
-(f) are cross-sectional views showing a method of manufacturing a FROM semiconductor device according to an embodiment of the present invention, and FIG. 5 is an explanatory view showing a state of a part of the same semiconductor device at an enlarged scale L7. 21... P-type silicon substrate, 22... element isolation film. 23... First thermal oxide film, 24... First polycrystalline silicon film, 25... Second thermal oxide film, 26... Second
27... Control gate electrode, 28... Second gate oxide film, 29... Floating dart electrode, 3o... Residual CVD oxide film, 3
0'... Dense CVD oxide film, 31... First
dirt oxide film, 32...N+ type source region, 33.
...N+ type drain region, 34.38...thermal oxide film,
35... PSG film, 36... Contact hole, 3
7...At wiring. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
１のダート電極材料膜、第２の絶縁膜及び第２のゲート
電極材料膜を順次積層する工程と、前記第２のダート電
極材料膜、第２の絶縁膜及び第１のダート電極材料膜を
順次パターニングして第２のゲート電極、第２のゲート
絶縁膜及び第１のダート電極を形成する工程と、全面に
絶縁性被膜を堆積した後、異方性エツチングにより第２
のダート電極、第２のダート絶縁膜及び第１のダート電
極側面に前記絶縁性被膜を残存させる工程と、露出した
前記第１の絶縁膜を選択的にエツチングして第１のダー
ト絶縁膜を形成する工程と、前記第２のダート電極及び
残存した絶縁性被膜にマスクとして利用し、基板と逆導
電型の不純物をイオン注入する工程と、酸化雰囲気中で
熱処理を行ない、前記不純物イオン注入層を活性化して
基板と逆導電型のソース、ドレイン領域を形成する工程
とを具備したことを特徴とする半導体装置の製造方法。a step of sequentially laminating a first insulating film, a first dart electrode material film, a second insulating film, and a second gate electrode material film on an element region of a semiconductor substrate of one conductivity type; A step of sequentially patterning an electrode material film, a second insulating film, and a first dirt electrode material film to form a second gate electrode, a second gate insulating film, and a first dirt electrode, and insulating the entire surface. After depositing the coating, a second
a step of leaving the insulating film on the side surfaces of the dirt electrode, the second dirt insulating film, and the first dirt electrode, and selectively etching the exposed first insulating film to form the first dirt insulating film. forming the second dirt electrode and the remaining insulating film as a mask, and ion-implanting an impurity having a conductivity type opposite to that of the substrate; and performing heat treatment in an oxidizing atmosphere to form the impurity ion-implanted layer. 1. A method of manufacturing a semiconductor device, comprising the step of activating a substrate to form source and drain regions of a conductivity type opposite to that of a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8857483A JPS59214265A (en) | 1983-05-20 | 1983-05-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8857483A JPS59214265A (en) | 1983-05-20 | 1983-05-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59214265A true JPS59214265A (en) | 1984-12-04 |
Family
ID=13946622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8857483A Pending JPS59214265A (en) | 1983-05-20 | 1983-05-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59214265A (en) |
-
1983
- 1983-05-20 JP JP8857483A patent/JPS59214265A/en active Pending
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