JPS57141932A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57141932A
JPS57141932A JP2753981A JP2753981A JPS57141932A JP S57141932 A JPS57141932 A JP S57141932A JP 2753981 A JP2753981 A JP 2753981A JP 2753981 A JP2753981 A JP 2753981A JP S57141932 A JPS57141932 A JP S57141932A
Authority
JP
Japan
Prior art keywords
pad
substrate
film
polycrystalline
patterning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2753981A
Other languages
Japanese (ja)
Inventor
Hiroshi Harigai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP2753981A priority Critical patent/JPS57141932A/en
Publication of JPS57141932A publication Critical patent/JPS57141932A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Abstract

PURPOSE:To prevent the breakage and the like of an Si substrate and reduce the capacity between a pad and the substrate by a method wherein a polycrystalline Si layer, having the surface area larger than the pad, is provided between the substrate and the pad consisting of a conductive metal film through the intermediary of first and second insulating films. CONSTITUTION:In an MOSIC and the like, for example, a polycrystalline Si film 3 is formed on the pad forming region of an Si substrate 1 whereon an element was formed covering the area wider than a pad electrode 5 by performing a patterning in a gate forming process. Then, after a PSG film 4, for example, has been deposited on the film 3, the pad 5 consisting of Al, for example, is evaporated, a patterning is performed, an over coating film 6 is coated, and an aperture is provided on the surface of the pad. Accordingly, the stress at the time of bonding is lessened, the deterioration and the like of junction characteristics due to the generation of cracks and the like can be prevented, and at the same time, the pad capacitance can be reduced, thereby enabling to perform a high-speed operation.
JP2753981A 1981-02-26 1981-02-26 Semiconductor device Pending JPS57141932A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2753981A JPS57141932A (en) 1981-02-26 1981-02-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2753981A JPS57141932A (en) 1981-02-26 1981-02-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57141932A true JPS57141932A (en) 1982-09-02

Family

ID=12223889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2753981A Pending JPS57141932A (en) 1981-02-26 1981-02-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57141932A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100855805B1 (en) * 2006-05-02 2008-09-01 세이코 엡슨 가부시키가이샤 Semiconductor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100855805B1 (en) * 2006-05-02 2008-09-01 세이코 엡슨 가부시키가이샤 Semiconductor device
US8614513B2 (en) 2006-05-02 2013-12-24 Seiko Epson Corporation Semiconductor device including a buffer layer structure for reducing stress
US8742601B2 (en) 2006-05-02 2014-06-03 Seiko Epson Corporation Semiconductor device including a buffer layer structure for reducing stress
US8952554B2 (en) 2006-05-02 2015-02-10 Seiko Epson Corporation Semiconductor device including a buffer layer structure for reducing stress
US9093334B2 (en) 2006-05-02 2015-07-28 Seiko Epson Corporation Semiconductor device including a buffer layer structure for reducing stress
US9331039B2 (en) 2006-05-02 2016-05-03 Seiko Epson Corporation Semiconductor device including a buffer layer structure for reducing stress
US9515043B2 (en) 2006-05-02 2016-12-06 Seiko Epson Corporation Semiconductor device including a buffer layer structure for reducing stress
US9842821B2 (en) 2006-05-02 2017-12-12 Seiko Epson Corporation Semiconductor device including semiconductor chip, wiring, conductive material, and contact part
US10103120B2 (en) 2006-05-02 2018-10-16 Seiko Epson Corporation Semiconductor device including a buffer layer structure for reducing stress
US10658325B2 (en) 2006-05-02 2020-05-19 Seiko Epson Corporation Semiconductor device including a buffer layer structure for reducing stress

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