JPS603152A - Manufacture of amorphous semiconductor device - Google Patents
Manufacture of amorphous semiconductor deviceInfo
- Publication number
- JPS603152A JPS603152A JP58111472A JP11147283A JPS603152A JP S603152 A JPS603152 A JP S603152A JP 58111472 A JP58111472 A JP 58111472A JP 11147283 A JP11147283 A JP 11147283A JP S603152 A JPS603152 A JP S603152A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thick
- layer
- amorphous semiconductor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 8
- 230000001681 protective effect Effects 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 39
- 239000004020 conductor Substances 0.000 description 9
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 6
- 229910052804 chromium Inorganic materials 0.000 description 6
- 239000011651 chromium Substances 0.000 description 6
- 238000007650 screen-printing Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 4
- 238000003384 imaging method Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14665—Imagers using a photoconductor layer
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、アモルファス半導体装置の製造方法にかかり
、特に厚膜回路を有する基板上への、アモルファス半導
体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing an amorphous semiconductor device, and particularly to a method of manufacturing an amorphous semiconductor device on a substrate having a thick film circuit.
近年、急速に実用化が進められているアモルファス半導
体は、大面積化が容易であり、大幅な組成の自由度を持
ち、電気的特性や光学的特性を、広範囲にわたって制御
できること等の長所を最大限に利用して、種々の分野へ
の応用が試みられている。Amorphous semiconductors, which have been rapidly put into practical use in recent years, are easy to make into large areas, have a large degree of freedom in composition, and have the ability to control electrical and optical properties over a wide range. Attempts are being made to utilize this technology to a limited extent and apply it to various fields.
その１つとして、例えば、固体撮像装置の制御回路部を
厚膜で構成すると共に、固体撮像素子等の能動素子部を
アモルファス半導体で構成したものが考えられている。As one example, it has been considered that the control circuit section of a solid-state imaging device is constructed from a thick film, and the active element section, such as a solid-state imaging device, is constructed from an amorphous semiconductor.
厚膜回路は、製造工数が少な（安価で、周囲条件に強く
、大電力に耐え得るという長所を有しており、アモルフ
ァス半導体との共存が望まれている反面、製造上の問題
から、上述の如きアモルファス半導体装置の実用化は困
難であった。Thick film circuits have the advantage of requiring fewer manufacturing steps (they are inexpensive, strong against ambient conditions, and can withstand large amounts of power), and are desired to coexist with amorphous semiconductors. However, due to manufacturing problems, It has been difficult to put such amorphous semiconductor devices into practical use.
ところで、この厚膜かもなる制御回路とアモルファス半
導体からなる固体撮像素子とを同一基板上に集積化せし
めるにあたり、従来は、以下に示すような方法が用いら
れていた。By the way, in order to integrate this thick-film control circuit and a solid-state imaging device made of an amorphous semiconductor on the same substrate, the following method has conventionally been used.
まずセラミック基板ｌ上に、第１の導体ペーストをイン
クとして使用し、スクリーン印刷法により印刷、および
焼成を行ない第１の導体層２を形成する。First, a first conductor layer 2 is formed on a ceramic substrate 1 by printing and firing using a first conductor paste as an ink using a screen printing method.
次いで、ガラスペーストをインクとして使用し、スクリ
ーン印刷法により、印刷および焼成を行ない絶縁層３を
形成する。Next, the insulating layer 3 is formed by printing and baking by screen printing using glass paste as ink.
更に、第１の等体層と同様に所定形状のスクリーンを用
℃・て、第２の導体層４をスクリーン印刷法により印刷
および焼成を行ない、第１図に示″″３−如く、厚膜制
御回路Ｃを形成づ−る。Furthermore, as with the first isoconductive layer, the second conductor layer 4 is printed and fired by the screen printing method using a screen having a predetermined shape at °C, so that the second conductor layer 4 has a thickness as shown in FIG. A membrane control circuit C is formed.
このようにして形成された厚膜がうなる制御回路部Ｃに
固体撮像素子部Ｓを並設すべ（蒸着及びフォトリングラ
フィによって、第２図に示す如く、下部電極５を形成す
る。A solid-state image sensor section S is arranged in parallel to the control circuit section C in which the thick film formed in this way is formed (a lower electrode 5 is formed by vapor deposition and photolithography, as shown in FIG. 2).
こののち、前記制御回路部Ｃをはじめとし、アモルファ
スシリコン層の堆積を不要とする部分の上に、メタルマ
スクと相称されている金属製の板状体を載置し、プラズ
マＣＶＤ法によって、第３図に示す如（、アモルファス
シリコン層７を選択的に堆積せしめろ。After that, a metal plate-like body, also known as a metal mask, is placed on the control circuit section C and other areas where the amorphous silicon layer does not need to be deposited, and the plasma CVD method is used to deposit the amorphous silicon layer. As shown in FIG. 3, an amorphous silicon layer 7 is selectively deposited.
そして、前記板状体６を排除したのち、通常の方法−蒸
着およ、びフォトリングラフイーにょって、上部電極８
を形成し、第４図に示す如く、アモルファス半導体装置
の形成かなされていた。Then, after removing the plate-like body 6, the upper electrode 8 is formed by a normal method - vapor deposition and photophosphorography.
As shown in FIG. 4, an amorphous semiconductor device was formed.
しかしながら、厚膜は、薄膜等に比べ、膜質がち密でな
いことから、このような方法によると、アモルファスシ
リコン層の着脱工程において、マスクとして使用されて
いる板状体６と導体層との間からシラン、水素等のガス
プラズマが入り込み、厚膜の膜質に損傷を与えたり、厚
膜とセラミック基板との間に、前記ガスプラズマによる
気泡が介入したりすることにより、厚膜の基板への密着
強度が低下１″る。従って、この厚膜回路に半導体チッ
プを塔載せしめるためのワイヤボンディング工程時には
、特に、腺の剥離がひんほんに発生し、歩留り低下の原
因となっていた。However, since thick films are not as dense as thin films, etc., this method does not allow for leakage between the plate-shaped body 6 used as a mask and the conductor layer during the process of attaching and detaching the amorphous silicon layer. Gas plasma such as silane or hydrogen may enter and damage the film quality of the thick film, or bubbles caused by the gas plasma may intervene between the thick film and the ceramic substrate, causing the thick film to adhere to the substrate. The strength is reduced by 1". Therefore, during the wire bonding process for mounting semiconductor chips on this thick film circuit, peeling of the glands frequently occurs, causing a decrease in yield.
本発明は、前記実情に鑑みてなされたもので、厚膜集積
回路基板上にアモルファス半導体装置を形成するにあた
り、厚膜回路に欠陥が発生するのを防止し、製造尖部り
を向上せしめることを目的とする。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to prevent defects from occurring in a thick film circuit and improve the sharpness of the manufacturing edge when forming an amorphous semiconductor device on a thick film integrated circuit substrate. With the goal.
本発明は、厚膜回路の形成された基板上に、アモルファ
ス半導体層を形成するにあたり、あらかじめ、この厚膜
回路を金属膜によって被覆シテ、厚膜回路を保護しつつ
、アモルファス半導体層を着膜したのち、この金属膜を
除去することにより、厚膜の剥離を防止しようとするも
のである。In the present invention, when forming an amorphous semiconductor layer on a substrate on which a thick film circuit is formed, the thick film circuit is coated with a metal film in advance, and the amorphous semiconductor layer is deposited while protecting the thick film circuit. After that, this metal film is removed to prevent the thick film from peeling off.
以下、本発明実施例の厚膜回路基板上へのアモルファス
半導体装置の製造方法について、図面を参照しつつ説明
する。Hereinafter, a method of manufacturing an amorphous semiconductor device on a thick film circuit board according to an embodiment of the present invention will be described with reference to the drawings.
ま１″、セラミック基板１上に、スクリーン印刷法によ
り、印刷、焼成し、第５図に示す如（、第１の導体であ
る金層２を形成する。1'' is printed and fired on the ceramic substrate 1 by a screen printing method to form a gold layer 2, which is a first conductor, as shown in FIG.
次いで、第６図に示′１−如（、スクリーン印刷法によ
り印刷、焼成し、絶縁性のガラス層３を形成する。Next, the insulating glass layer 3 is formed by printing and baking by a screen printing method as shown in FIG. 6.
更に、第７図に示す如く、スクリーン印刷法により、印
刷、焼成し、第２の導体である金層４を形成する。Furthermore, as shown in FIG. 7, printing and firing are performed by a screen printing method to form a gold layer 4, which is a second conductor.
このようにして形成された厚膜制御回路Ｃを有する基板
全体に、蒸着法によって膜厚４Ｕ００Åのクロム層を着
膜し、第８図に示す如（、フォトリングラフィによって
下部のクロム電極５および厚膜制御回路の保護膜９とな
る部分を除（不要部のクロム層を除去する。ここで、下
部電極５は前記厚膜制御回路と相互接続される様な形状
にバターニングするものとする。A chromium layer with a thickness of 4U00 Å was deposited on the entire substrate having the thick film control circuit C formed in this way by vapor deposition, and the lower chromium electrode 5 and The portion that will become the protective film 9 of the thick film control circuit is removed (unnecessary portions of the chromium layer are removed. Here, the lower electrode 5 is patterned into a shape that will be interconnected with the thick film control circuit). .
そして更に、第９図に示す如（、この上に金属製の板状
体６を載置し、プラズマＣＶＤ法により、水素化アモル
ファスシリコン層７を選択的に堆積せしめる。この水素
化アモルファスシリコン層の膜厚は１μｍである。Further, as shown in FIG. 9, a metal plate 6 is placed thereon, and a hydrogenated amorphous silicon layer 7 is selectively deposited by plasma CVD. The film thickness is 1 μm.
次いで前記板状体６を排除した後、フォ）！ソグラフィ
により厚膜印刷回路上のクロムから１よる保護膜９をエ
ツチング除去する１、最後に、第１０図に示ず如（、メ
タルマスク（図示せず）を介し、上部電極として所定形
状の酸化インジウム錫′祇極を約０１μｍの膜厚で着膜
する。Next, after removing the plate-shaped body 6, 4)! The protective film 9 of 1 is etched away from the chromium on the thick film printed circuit by lithography 1. Finally, as shown in FIG. An indium tin film is deposited to a thickness of about 0.1 μm.
コ（７） ヨ５にして、水素化アモルファスシリコン層
からなる固体撮像素子部Ｓと厚膜制御部Ｃとよりなる半
導体装置が形成される。(7) In step 5, a semiconductor device consisting of a solid-state image sensor section S made of a hydrogenated amorphous silicon layer and a thick film control section C is formed.
この半導体装置における厚膜回路は基板との密着性が極
めて良好であり、経時的に安定である上、この回路上に
、シフトレジスタ等の半導体チップを塔載するにあたり
、ダイボンディング、ワイヤボンティングを行なっても
厚膜の剥離を生じることもなく、実装にあたっての製造
歩留りが極めて良好である。The thick film circuit in this semiconductor device has extremely good adhesion to the substrate and is stable over time.In addition, when mounting semiconductor chips such as shift registers on this circuit, die bonding, wire bonding, etc. Even if this is done, the thick film does not peel off, and the manufacturing yield during mounting is extremely good.
なお、実施例においては、厚膜回路の保護膜として下部
電極形成工程で％ｆ膜されたクロム膜を利用したが、別
工程で金等の異なる材質の金属膜を形成してもよい。In the embodiment, a chromium film deposited in the lower electrode forming step was used as a protective film for the thick film circuit, but a metal film made of a different material such as gold may be formed in a separate step.
また、実施例においては、固体撮像装置について説明し
たが、薄膜トランジスタ回路、太陽電池をはじめとし、
他方面への適用も可能である。In addition, although solid-state imaging devices have been described in the examples, there are other applications including thin film transistor circuits and solar cells.
Application to the other side is also possible.
１１どで １
〔発明の効果〕
以上、説明してきたように、本発明によれば、アモルフ
ァス半導体層の形成前に厚膜回路部を金属膜で被覆し、
保護しておくことにより、厚膜回路に欠陥を生ぜしめる
ことな（、アモルファス半導体層を堆積し得、製造歩留
りの良好な半導体装置の提供が可能となる１、11.1 [Effects of the Invention] As explained above, according to the present invention, the thick film circuit portion is covered with a metal film before the formation of the amorphous semiconductor layer,
By protecting it, it is possible to deposit an amorphous semiconductor layer without causing defects in the thick film circuit, and it is possible to provide a semiconductor device with a good manufacturing yield.
第１図乃至第４図は、従来のアモルファス半導体装置の
製造工程を示Ｊ−図、第５図乃至第１０図は、本発明実
施例のアモルファス半導体装置の製造工程を示す図であ
る。
Ｉ・・・セラミック基板、２・・・第１の導体層（金）
？！Ｊ）、３・・・ガラス層（絶縁ハｉ）、４・・・第
２の導体層（金層）、５・・・下部′電極（クロム電極
）、６・−＆状体（メタルマスク）、７・・・アモルフ
ァスシリコン層、８・・・上部電極（ＩＴＯ電極）、９
・・・保護膜、Ｃ・・・制御回路部、Ｓ・・・固体撮像
素子部。
１曽１
ン１ｊ ｌ
４
第５図
第６図
ス
第７図
乙
第８図
第９図
第１０図1 to 4 are diagrams showing the manufacturing process of a conventional amorphous semiconductor device, and FIGS. 5 to 10 are diagrams showing the manufacturing process of an amorphous semiconductor device according to an embodiment of the present invention. I... Ceramic substrate, 2... First conductor layer (gold)
? ! J), 3...Glass layer (insulation high i), 4...Second conductor layer (gold layer), 5...Lower' electrode (chromium electrode), 6...-& shaped body (metal mask ), 7... Amorphous silicon layer, 8... Upper electrode (ITO electrode), 9
...Protective film, C...Control circuit section, S...Solid-state image sensor section. 1 So 1 N 1j l 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10
Claims (1)
子を形成１−るにあたり、アモルファス半導体の着膜工
程に先立ち、あらかじめ、前記厚膜回路素子を金属膜で
被覆し、保護する工程を有することを特徴とするアモル
ファス半導体装置の製造方法。In forming an amorphous semiconductor element on a substrate having a thick film circuit element, the method includes a step of covering and protecting the thick film circuit element with a metal film in advance, prior to the step of depositing the amorphous semiconductor. A method for manufacturing a characterized amorphous semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58111472A JPS603152A (en) | 1983-06-21 | 1983-06-21 | Manufacture of amorphous semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58111472A JPS603152A (en) | 1983-06-21 | 1983-06-21 | Manufacture of amorphous semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS603152A true JPS603152A (en) | 1985-01-09 |
| JPH028465B2 JPH028465B2 (en) | 1990-02-23 |
Family
ID=14562109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58111472A Granted JPS603152A (en) | 1983-06-21 | 1983-06-21 | Manufacture of amorphous semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS603152A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04129035U (en) * | 1991-05-17 | 1992-11-25 | ホシザキ電機株式会社 | Refrigerant condenser support structure |
-
1983
- 1983-06-21 JP JP58111472A patent/JPS603152A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04129035U (en) * | 1991-05-17 | 1992-11-25 | ホシザキ電機株式会社 | Refrigerant condenser support structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH028465B2 (en) | 1990-02-23 |
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