JPS60117684A - Manufacture of amorphous si solar battery - Google Patents
Manufacture of amorphous si solar batteryInfo
- Publication number
- JPS60117684A JPS60117684A JP58224112A JP22411283A JPS60117684A JP S60117684 A JPS60117684 A JP S60117684A JP 58224112 A JP58224112 A JP 58224112A JP 22411283 A JP22411283 A JP 22411283A JP S60117684 A JPS60117684 A JP S60117684A
- Authority
- JP
- Japan
- Prior art keywords
- film
- mask
- substrate
- electrodes
- stainless steel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021417 amorphous silicon Inorganic materials 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 14
- 238000002161 passivation Methods 0.000 claims abstract description 6
- 239000002952 polymeric resin Substances 0.000 claims description 14
- 229920003002 synthetic resin Polymers 0.000 claims description 14
- 238000005755 formation reaction Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 42
- 239000010935 stainless steel Substances 0.000 abstract description 15
- 229910001220 stainless steel Inorganic materials 0.000 abstract description 15
- 239000010409 thin film Substances 0.000 abstract description 13
- 229920005989 resin Polymers 0.000 abstract description 10
- 239000011347 resin Substances 0.000 abstract description 10
- 229920001721 polyimide Polymers 0.000 abstract description 4
- 239000004642 Polyimide Substances 0.000 abstract description 3
- 229920000642 polymer Polymers 0.000 abstract description 2
- 229920006254 polymer film Polymers 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
- H01L31/03921—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate including only elements of Group IV of the Periodic Table
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は非晶質シリコン太陽電池の製造方法に関する。[Detailed description of the invention] [Field of application of the invention] The present invention relates to a method for manufacturing an amorphous silicon solar cell.
非晶質シリコン太陽電池は、透明電極と非晶質シリコン
と背面電極とよりなるセル１個当り螢光打丁で得られる
開放電圧が約０．７ｖ前後である。An amorphous silicon solar cell has an open-circuit voltage of about 0.7 V obtained with a fluorescent knife per cell consisting of a transparent electrode, amorphous silicon, and a back electrode.
そこで太陽電池を例えば電卓などの電源として用いた場
合、少なくとも３個以上のセルを直列接続する必要があ
る。この直列接続は透明電極および背面電極のパタン形
成時に１つの基板上ｔこ形成されるが、前記透明電極と
背面電極を種々の目的に応じたパタンにする方法には、
次の２通りの方法がある。Therefore, when a solar cell is used as a power source for, for example, a calculator, it is necessary to connect at least three or more cells in series. This series connection is formed on one substrate when forming the pattern of the transparent electrode and the back electrode, but methods for forming the transparent electrode and the back electrode into patterns according to various purposes include:
There are two methods:
第１の方法は、各電極の成膜後にホトエツチングにより
所望のバタンにする方法で、現在一般的に行なわれてい
る方法である。しかし、この方法はコストが高く、また
電極、半導体などを一貫成膜するのは不可能である。The first method is to form a desired pattern by photoetching after forming each electrode, and is a method commonly used at present. However, this method is expensive, and it is impossible to form electrodes, semiconductors, etc. in an integrated manner.
第２の方法は、成膜時に所望のパタンをくり抜いたマス
クを基板に密着させて行なうマスク成膜による方法であ
る。この方法は特に可撓性基板を用いた太陽電池の作製
に適し、−貫成膜化が容易で、製造コストも低くするこ
とができる。しかし、この方法は次のような欠点を有す
る。The second method is a method of mask film formation in which a mask with a desired pattern cut out is brought into close contact with the substrate during film formation. This method is particularly suitable for the production of solar cells using flexible substrates; - through-film formation is easy; and manufacturing costs can be reduced. However, this method has the following drawbacks.
電極や半導体、パッシベーション−などのパタンをマス
ク成膜により形成する場合、マスクと基板は十分に密着
していないと、蒸発粒子の回り込が生じ、所望の特性が
得、られなくなることがある。When forming patterns for electrodes, semiconductors, passivation, etc. by mask film formation, if the mask and substrate are not in close contact with each other, evaporated particles may wrap around, making it impossible to obtain desired characteristics.
そこで、マスクと基板が十分密着するようにさせると、
マスクが、基板に絶縁層として形成された樹脂薄膜ある
いは既に成膜された膜上に傷を生じさせるという問題が
生じる。傷が発生すると、基板と背面電極および透明電
極と背面電極間に電気的短絡が生じ、太陽電池としての
出力が低下したり、場合によっては全く出力が得られな
くなったりする°。Therefore, by making sure that the mask and substrate are in close contact with each other,
A problem arises in that the mask causes scratches on the resin thin film formed as an insulating layer on the substrate or on the film that has already been formed. When scratches occur, an electrical short circuit occurs between the substrate and the back electrode, and between the transparent electrode and the back electrode, resulting in a decrease in the output of the solar cell, or in some cases, no output at all.
本発明の目的は、基板あるいは既に成膜された膜上への
傷を防止することができる非晶質シリコン太陽電池の製
造方法を提供するにある。An object of the present invention is to provide a method for manufacturing an amorphous silicon solar cell that can prevent damage to a substrate or a film that has already been formed.
本発明は、基板上に背ＷＩ電極のバタン、非晶質シリコ
ン膜、透明電極のバタンおヨヒバッシヘーション膜のう
ち少なくとも１つをマスク成膜してなる非晶質シリコン
太陽電池の製造方法において、前記マスク成膜のうち、
少なくとも１つのマスク成膜を、少なくとも前記基板側
の面に高分子樹脂薄膜をコートしたマスクを用いて行な
うことを特徴とする。The present invention provides a method for manufacturing an amorphous silicon solar cell in which at least one of a back WI electrode, an amorphous silicon film, and a transparent electrode is deposited on a substrate using a mask. In the mask film formation,
The method is characterized in that at least one mask film formation is performed using a mask whose surface on at least the substrate side is coated with a thin polymer resin film.
以下、本発明の一実施例を第１図により説明する。可撓
性かつ耐熱性を有する例えば板厚約ｉｏ。An embodiment of the present invention will be described below with reference to FIG. For example, a plate having a thickness of about io, which is flexible and heat resistant.
μｍのステンレス基板１の上面に耐熱性を有する高分子
樹脂薄膜２、例えばボリイξド系樹脂を厚さ約２〜１０
μｍ程度に形成する。この場合、膜形成方法としては、
液状の樹脂をスプレもしくはディップ法等により一様ｌ
こ塗布し、これを約３５０℃の高温度で硬化して形成す
る。次ニ樹脂薄膜２上ｌこステンレスのマスク（図示せ
ず）を密着させてステンレスをスパッタすることにより
膜厚約１０００〜２０００Ａ程度の背面電極３１，３２
．３３．３４をそれぞれ所定間隔でマスク成膜する。A heat-resistant polymeric resin thin film 2, such as a polyamide resin, is coated on the top surface of a stainless steel substrate 1 with a thickness of approximately 2 to 10 μm.
It is formed to a size of approximately μm. In this case, the film formation method is as follows:
Uniformly apply liquid resin by spraying or dipping.
This is applied and cured at a high temperature of about 350°C. Next, a stainless steel mask (not shown) is placed on the thin resin film 2 and stainless steel is sputtered onto the back electrodes 31 and 32 to a film thickness of about 1000 to 2000 Å.
．． 33 and 34 are formed using masks at predetermined intervals.
続いて各背面電極３１〜３４上にプラズマＣｖＤにより
基板温度約２５０℃でｐ、ｉ、ｎまたはｎ１１、ｐの顔
に非晶質シリコン膜４をステンレスのマスクを密着させ
゛Ｃマスク成膜する。次に前記各背面電極３１〜３４と
対向する非晶質シリコン膜４上には、隣接する各背面電
極３１〜３４の一端に接続するようにＩｎ、０．を約８
００λの厚さにステンレスのマスクを密着させてスパッ
タして透明電極５１，５２．５３．５４をマスク成膜す
る。Subsequently, an amorphous silicon film 4 is formed on each of the back electrodes 31 to 34 by plasma CVD at a substrate temperature of about 250° C. by closely adhering a stainless steel mask to the face of p, i, n or n11, p. . Next, on the amorphous silicon film 4 facing each of the back electrodes 31 to 34, In, 0.0. about 8
Transparent electrodes 51, 52, 53, and 54 are formed by sputtering with a stainless steel mask in close contact with a thickness of 00λ.
最後に、透明電極５１〜５４上にステンレスのマスクを
密着させて８ｉ０．を約２００ＯＡの厚さにスパッタし
てパッシベーション膜６をマスク成膜し、４個直列接続
された非晶質シリコン太陽電池を完成した。この場合、
４個の非晶質シリコン太陽電池の相互の接続は各透明電
極５１〜５４の電極パターンの形成と同時に形成され、
また背面電極３４の一端部と透明電極５１の一端部には
出力電圧取り出し用の端子３４ａ、５１ａがそれぞれ形
成されている。Finally, a stainless steel mask is brought into close contact with the transparent electrodes 51 to 54 and 8i0. A passivation film 6 was formed using a mask by sputtering to a thickness of about 200 OA, thereby completing four amorphous silicon solar cells connected in series. in this case,
The mutual connection of the four amorphous silicon solar cells is formed simultaneously with the formation of the electrode pattern of each transparent electrode 51 to 54,
Further, terminals 34a and 51a for output voltage extraction are formed at one end of the back electrode 34 and one end of the transparent electrode 51, respectively.
ところで、本発明においては、背面電極３１〜３４のマ
スク成膜、非晶質シリコン膜４のマスク成膜、透明電極
５１〜５４のバタンのマスク成膜右よびパッシベーショ
ン膜６のマスク成膜は、少なくとも基板１側の面に高分
子樹脂薄膜例えばポリイｉドＪｊｌＮ１９＄、 ！、
ａ電鵜麿コートＩ、ナーマス々ん用いて行なう。By the way, in the present invention, the mask deposition of the back electrodes 31 to 34, the mask deposition of the amorphous silicon film 4, the mask deposition of the transparent electrodes 51 to 54, and the mask deposition of the passivation film 6 are as follows. At least on the surface of the substrate 1 side, a thin polymer resin film such as polyimide JjlN19$ is applied! ,
a) Perform using Den Umaro Coat I and Namasu.
今、１例として、背面電極３１〜３４のマスク成膜時の
概略図を第２図に示す。真空槽１０内には基板ホルダ１
１が懸垂されており、樹脂薄膜２が形成されたステンレ
ス基板１および高分子樹脂薄膜１２がコートされたマス
ク１３が前記基板ホルダ１１の下面に保持されている。As an example, FIG. 2 shows a schematic diagram of the back electrodes 31 to 34 during mask film formation. A substrate holder 1 is placed inside the vacuum chamber 10.
1 is suspended, and a stainless steel substrate 1 on which a resin thin film 2 is formed and a mask 13 coated with a polymeric resin thin film 12 are held on the lower surface of the substrate holder 11.
そこで、基板ホルダ１１の下方に配設されたターゲット
１４よりステンレスをスパッタすると、第１図に示す背
面電極３１〜３４がマスク１３を介してマスク成膜され
る。Therefore, when stainless steel is sputtered from a target 14 disposed below the substrate holder 11, the back electrodes 31 to 34 shown in FIG. 1 are formed through the mask 13.
こノヨウに、マスク１３にコートした高分子樹脂膜１２
をステンレス基板ｌ上の樹脂薄膜２に密着させるので、
樹脂薄膜２への傷は著しく抑止され、ステンレス基板ｌ
と背面電極３１〜３４の短絡は完全ｌζ防止される。前
記のようｌこ、他の各層４．５１〜５４．６のマスク成
膜も高分子樹脂薄膜ヲコートしたマスクを用いて行なえ
ば、背向・１極３１〜３４と透明電極５１〜５４間の短
絡も完全に防止される。Additionally, the polymer resin film 12 coated on the mask 13
Since it is brought into close contact with the resin thin film 2 on the stainless steel substrate l,
Scratches on the resin thin film 2 are significantly suppressed, and the stainless steel substrate l
A short circuit between the back electrodes 31 to 34 is completely prevented. As mentioned above, if the mask film formation of each of the other layers 4.51 to 54.6 is also performed using a mask coated with a thin polymer resin film, the formation of the mask between the back-facing single poles 31 to 34 and the transparent electrodes 51 to 54 is possible. Short circuits are also completely prevented.
本実施例の場合、セル１個（受光面積ｌｃｒ＆）当りの
開放電圧はｏ、６１’であり、セル間の絶縁不良による
損失は全く生じなく、また各セル共０．６６ｖが得られ
、１つのセル内での電極間短絡による不良も従来すこ比
べ大幅に減少し、２００１ｕｘの螢光打丁において、約
２．６４ｖ（０，６６Ｘ４Ｖ’）の開放電圧と約２０μ
λ７−の短絡電流が得られた。In the case of this example, the open circuit voltage per cell (light-receiving area lcr&) is o, 61', no loss occurs due to poor insulation between cells, and 0.66 V is obtained for each cell, 1 The number of defects caused by short circuits between electrodes within one cell has also been significantly reduced compared to the conventional method, and the open circuit voltage of approximately 2.64V (0.66X4V') and approximately 20 μ
A short circuit current of λ7- was obtained.
なお、前記実施例においては、マスクにコートした高分
子樹脂薄膜の厚さは５μｍの場合について説明したが、
これに限定されるものではなく、０．５〜３００μｍの
範囲であれば良い。この場合、膜厚が０．５μｍ以下で
は傷の抑止に効果がなくな、す、３００μｍ以上ではこ
れ以上厚くしても単に膜厚を厚くするのみで意味がなく
、真空中での放出ガス量も問題になる。従って、実際の
使用に際しては、２〜２０μ扉程度が最適である。また
ポリイミド系樹脂に限らず、シリコーン樹脂等を用いて
も同様の効果が得られる。またマスクの材質もステンレ
スに限定されるものではない。In the above example, the thickness of the polymer resin thin film coated on the mask was 5 μm.
It is not limited to this, but may be in the range of 0.5 to 300 μm. In this case, if the film thickness is less than 0.5 μm, it will not be effective in preventing scratches, and if it is more than 300 μm, there is no point in increasing the film thickness, and the amount of gas released in a vacuum. is also a problem. Therefore, in actual use, a door size of about 2 to 20 μm is optimal. Moreover, the same effect can be obtained not only by using polyimide resin but also by using silicone resin or the like. Furthermore, the material of the mask is not limited to stainless steel.
また、前記実施例に示すように各層のマスク成膜を全て
高分子樹脂薄膜がコートされたマスクで行なった方が効
果的であることはいうまでもないが、少なくとも一つの
層についＣのみ高分子樹脂薄膜がコートされたマスクで
行なっても従来より良好な効果が得られる。It goes without saying that it is more effective to perform mask film formation for each layer using a mask coated with a thin polymer resin film as shown in the above example, but it is also possible to Even if the mask is coated with a molecular resin thin film, better effects can be obtained than in the past.
上記実施例の構造の素子においＣ一つの層のみ高分子樹
脂薄膜をコートしたマスクを使用するならば、透明電極
５１〜５４にこれを適用するのが最も効果的である。こ
れは、その前に成膜された非晶質シリコン膜が傷に対し
て最も敏感で、特性に悪影響を及ぼすからである。If a mask in which only one layer of C is coated with a thin polymer resin film is used in the device having the structure of the above embodiment, it is most effective to apply this to the transparent electrodes 51 to 54. This is because the amorphous silicon film formed before that is most sensitive to scratches, which adversely affects the characteristics.
また、前記実施例においては、基板］とし°Ｃ１ステン
レス基板を用いた場合についで説明したが、本発明はこ
れに限定されるものではなく、金属基板、例えばＦｅ−
Ｎｉ合金板または高分子樹脂膜として例えばポリイミド
系のカプトン（商品名）を用いても同様の効果が得られ
る。また可撓性基板に限定さイＬなく、例えばガラス基
板を用いてもよい。また基板の厚さも特ｌこ１００μｍ
ｒＬ４こ限定されるものではない。Further, in the above embodiment, a case was explained in which a °C1 stainless steel substrate was used as the substrate, but the present invention is not limited to this, and a metal substrate, for example, a Fe-
Similar effects can be obtained by using, for example, polyimide Kapton (trade name) as the Ni alloy plate or polymer resin film. Further, the substrate is not limited to a flexible substrate, and for example, a glass substrate may be used. Also, the thickness of the substrate is 100 μm.
It is not limited to rL4.
また、前記実施例においては、基板ｌ上に形成する高分
子樹脂薄膜２は、約２〜１０μｍの厚さに形成した場合
について説明したが、この膜厚は基板の板厚によっても
異なるので、概略０．１〜１００μｍの範囲で形成すれ
ばよい。この場合、膜厚は０．１μｍ以下では絶縁性が
得られず、１００μｍ以上となると折り曲げたときに膜
剥れが生ずる。また、膜特性、生産性などの点から考慮
して２〜ｌＯμｍの範囲が最適である。Further, in the above embodiment, the case where the polymer resin thin film 2 formed on the substrate l was formed to have a thickness of about 2 to 10 μm was explained, but since this film thickness varies depending on the thickness of the substrate, What is necessary is just to form it in the range of about 0.1-100 micrometers. In this case, if the film thickness is 0.1 μm or less, insulation cannot be obtained, and if it is 100 μm or more, the film will peel off when it is bent. Further, in consideration of film properties, productivity, etc., a range of 2 to 10 μm is optimal.
本発明によれば、少なくとも一つの層を高分子樹脂薄膜
をコートしたマスクを用いてマスク成膜してなるので、
膜傷が著しく抑止され、基板と背面電極間または背面電
極と透明電極間の短絡を抑制することができ、信頼性の
高い高品質、高性能の非晶質シリコン太陽電池が得られ
る。According to the present invention, since at least one layer is formed using a mask coated with a thin polymer resin film,
Film scratches are significantly suppressed, short circuits between the substrate and the back electrode or between the back electrode and the transparent electrode can be suppressed, and a highly reliable, high-quality, high-performance amorphous silicon solar cell can be obtained.
第１図は本発明の方法により作製した非晶質シリコン太
陽電池の一実施例を示し、（ａ）は要部の一部破断乎面
図、（ｂ）はｔａｌのＡ−Ａ線にそう断面図、第２図は
マスク成膜状態の一実施例を示す概略図である。
１・・・ステンレス基板、 ２・・・高分子ｓｔｎ旨薄
膜、３１〜３４・・・背面電極、４・・・非晶質シＩＪ
コン膜、 ５１〜５４・・・透明電極、 １２・・・高
分子樹脂薄膜、 】３・・・マスク。
第１図
（０）
（ｂ）
第２図FIG. 1 shows an example of an amorphous silicon solar cell produced by the method of the present invention, (a) is a partially cutaway view of the main part, and (b) is a view taken along line A-A of tal. The cross-sectional view and FIG. 2 are schematic diagrams showing an example of a mask film forming state. DESCRIPTION OF SYMBOLS 1... Stainless steel substrate, 2... Polymer stn thin film, 31-34... Back electrode, 4... Amorphous steel IJ
Con film, 51-54...Transparent electrode, 12...Polymer resin thin film, ]3...Mask. Figure 1 (0) (b) Figure 2
Claims (1)
極のバタンおよびパッシベーション膜のうち少なくとも
１つをマスク成膜してなる非晶質シリコン太陽電池の製
造方法において、前記マスク成膜のうち、少なくとも１
つのマスク成膜を、少なくとも前記基板側の面に高分子
樹脂薄膜をコートしたマスクを用いて行なうことを特徴
とする非晶質シリコン太陽電池の製造方法。In a method for manufacturing an amorphous silicon solar cell, in which at least one of a back electrode layer, an amorphous silicon film, a transparent electrode layer, and a passivation film are formed on a substrate using a mask, , at least 1
1. A method for manufacturing an amorphous silicon solar cell, characterized in that two mask film formations are performed using a mask whose surface on at least the substrate side is coated with a thin polymer resin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58224112A JPS60117684A (en) | 1983-11-30 | 1983-11-30 | Manufacture of amorphous si solar battery |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58224112A JPS60117684A (en) | 1983-11-30 | 1983-11-30 | Manufacture of amorphous si solar battery |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60117684A true JPS60117684A (en) | 1985-06-25 |
Family
ID=16808718
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58224112A Pending JPS60117684A (en) | 1983-11-30 | 1983-11-30 | Manufacture of amorphous si solar battery |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60117684A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6441276A (en) * | 1987-08-07 | 1989-02-13 | Fuji Electric Co Ltd | Forming method for thin film |
| EP0481094A1 (en) * | 1990-05-07 | 1992-04-22 | Canon Kabushiki Kaisha | Solar cell |
| JP2006296188A (en) * | 2005-03-18 | 2006-10-26 | Hitachi Industrial Equipment Systems Co Ltd | Multiple phase claw-pole type motor |
-
1983
- 1983-11-30 JP JP58224112A patent/JPS60117684A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6441276A (en) * | 1987-08-07 | 1989-02-13 | Fuji Electric Co Ltd | Forming method for thin film |
| EP0481094A1 (en) * | 1990-05-07 | 1992-04-22 | Canon Kabushiki Kaisha | Solar cell |
| EP0481094A4 (en) * | 1990-05-07 | 1994-03-30 | Canon Kabushiki Kaisha | |
| JP2006296188A (en) * | 2005-03-18 | 2006-10-26 | Hitachi Industrial Equipment Systems Co Ltd | Multiple phase claw-pole type motor |
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