JPS6142943A - Manufacture of complex semiconductor device - Google Patents

Manufacture of complex semiconductor device

Info

Publication number
JPS6142943A
JPS6142943A JP16507184A JP16507184A JPS6142943A JP S6142943 A JPS6142943 A JP S6142943A JP 16507184 A JP16507184 A JP 16507184A JP 16507184 A JP16507184 A JP 16507184A JP S6142943 A JPS6142943 A JP S6142943A
Authority
JP
Japan
Prior art keywords
resist
thin film
metal thin
semiconductor element
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16507184A
Other languages
Japanese (ja)
Inventor
Shoji Takishima
滝島 昭二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP16507184A priority Critical patent/JPS6142943A/en
Publication of JPS6142943A publication Critical patent/JPS6142943A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

PURPOSE:To improve an ohmic of wiring connected straddling on the surface of both elements by changing a semiconductor element and a function element into an integral structure through an insulating material for each surface of both elements to be the same in height and by forming a fine width wiring straddling on the surface of both elements with a photolithography after forming a metal thin film on the surface of both elements. CONSTITUTION:A surface of an integral structure 12 is fixed on a supporting substrate 1 through a bonding agent 13. The surface leaving a part of an electrode 5 of a semiconductor element 3 is covered with the first resist 14. A metal thin film 15 such as an aluminium is accumulated on a surface of the integral structure 12 including the first resist 14. The first resist 14 and a metal thin film 15 on it are eliminated with the lift off method. The metal thin film 15 left and a desired part of the surface of the electrode 5 is covered with the second resist 16 again, and the metal thin film 15 selectively etched using the second resist 16 as a mask.

Description

【発明の詳細な説明】 本発明は、半導体素子と機能素子とが共通支持基板上に
配置された複合半導体装置の製造方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a composite semiconductor device in which a semiconductor element and a functional element are arranged on a common support substrate.

各雅半導体素子忙おける半導体キャリア(いわゆるバル
ク波)と機能素子飼えば弾性表面波素子における弾性表
面波とを結合させることにより、減辰、増幅等の線型結
合あるいはコンボリューション、コリレーション等の非
線型結合現象を利用した表面波増幅器や表面波コンボル
バ等の研究、開発が盛んに行われている。
By coupling the semiconductor carrier (so-called bulk wave) in each semiconductor element with the surface acoustic wave in the functional surface acoustic wave element, linear coupling such as attenuation and amplification, or non-linear coupling such as convolution and correlation can be achieved. Research and development of surface wave amplifiers, surface wave convolvers, etc. that utilize linear coupling phenomena is being actively conducted.

このためには半導体素子を構成するシリコン、1−V族
金属間化合物等の半導体基板と機能素子を構成″1−る
ニオブ酸リチウム(LtNbO3)、タンタル酸リチウ
ム(LiTa0a )等の圧電基板とZ一体的に組み合
わせることが行われる。第り図はこのようにして得られ
7:複合半導体装置の構造を示すもので、工は支持基板
、2はリード、3は半導体素子、4は弾性表面波素子、
・5,6は上記素子3゜4表面に各々設けられた1!極
、7は電極5,6同士あるいは上記電極5,6とリード
2間を接続するボンディングワイヤで、半導体素子3お
よび弾性表面波素子4は支持基板l上に配置されている
For this purpose, a semiconductor substrate such as silicon or 1-V group intermetallic compound that constitutes the semiconductor element, a piezoelectric substrate such as lithium niobate (LtNbO3) or lithium tantalate (LiTa0a), and Z Figure 7 is obtained in this way and shows the structure of a composite semiconductor device, where 5 is a support substrate, 2 is a lead, 3 is a semiconductor element, and 4 is a surface acoustic wave. element,
・5 and 6 are 1! provided on the 3゜4 surface of the above element, respectively. A pole 7 is a bonding wire that connects the electrodes 5 and 6 or between the electrodes 5 and 6 and the lead 2. The semiconductor element 3 and the surface acoustic wave element 4 are arranged on a support substrate l.

しかしながらこのように異種材料から成る基板χ一体的
に組み合わせるには製造上問題がある。
However, there are manufacturing problems in integrally combining the substrates χ made of different materials in this way.

例えば上記弾性表面波素子4表面に形成される電極6は
、1〜2μパタ一ン幅ですだれ状に設けられたトランス
ジューサと称される弾性表面波素子生させるためのもの
でアルミニウム等で構成され、−男手導体素子3表面に
は5〜6μパタ一ン幅の電極5が形成され、これら両を
極5〜6間は上記ボンティングワイヤ7によって接続さ
れるが、上記のように微細幅の′FiL&同士でワイヤ
ボンディングを良好九行なうのは極めて困難である。こ
のため特殊な工程を採用せざるを得なくなりコストアッ
プとなる。
For example, the electrode 6 formed on the surface of the surface acoustic wave element 4 is for producing a surface acoustic wave element called a transducer, which is provided in a webbing shape with a pattern width of 1 to 2 microns, and is made of aluminum or the like. , - On the surface of the male conductor element 3, an electrode 5 with a width of 5 to 6 micrometers is formed, and the electrodes 5 and 6 are connected by the bonding wire 7, as described above. It is extremely difficult to perform good wire bonding between 'FiL&'. Therefore, a special process has to be adopted, which increases costs.

本発明は以上の問題に対処してなされたもので、特殊な
工程ン採用することな(半導体素子と機能素子との各々
表面に跨った配線を容易に形成し得るように構成した複
合半導体装置の製造方法乞提供することを目的とするも
のである。
The present invention has been made in response to the above problems, and is a composite semiconductor device configured to easily form wiring spanning the surfaces of semiconductor elements and functional elements (without employing special processes). The purpose of the present invention is to provide a method for manufacturing the same.

このような目的を達成するための本発明の特徴とすると
ころは、 (A)  半導体素子と機能素子とを各々表面が同一高
さとなるように絶縁物乞介して一体化する工程、(均 
一体化構造における半導体素子表面の所望部ン覆うよう
に第1のレジストを形成する工程、(E)ilのレジス
トを含む一体化構造表面に金属R膜を形成する工程、 (Dmlのレジストと共に金属薄膜の一部を除去する工
程、 (E)  Iliりの金属薄膜および半導体素子表面の
所望部ン覆うよう忙第2のレジストヲ形成する工程、(
F)M2のレジスIf’マスクとして金属薄膜を選択的
に除去することにより半導体素子と機能素子との各々表
面に跨った配+161a’形成する工程、を含む複合半
導体装置の製造方法にある、ものである。
The features of the present invention for achieving such objects are as follows: (A) a step of integrating the semiconductor element and the functional element with an insulator interposed so that their respective surfaces are at the same height;
a step of forming a first resist so as to cover a desired portion of the surface of the semiconductor element in the integrated structure; a step of forming a metal R film on the surface of the integrated structure including the resist of (E)il; a step of removing a portion of the thin film; (E) a step of forming a second resist so as to cover a desired portion of the metal thin film and the surface of the semiconductor element;
F) A method for manufacturing a composite semiconductor device, including the step of forming a wiring 161a' spanning the surfaces of a semiconductor element and a functional element by selectively removing a metal thin film as a M2 resist If' mask. It is.

以下図面?参照して本発明実施ν!I’a[明する。Is the drawing below? Implement the present invention with reference to ν! I'a [to clarify.

第2図(ω〜(g)は本発明実施例に、よる複合半導体
装置の製造方法ン工程順に示す断面図で、以下工程J順
に説明する◎ 工程〔A〕:第2図(a)のように、支持台8上にフィ
ルム9を用意しこのフィルム9に所望の回路素子が設け
られて電極5を備える千棉体素子3と圧電基板から成る
弾性衣面欧素子4とを隙間lO乞介して田着させ、この
隙間10に絶縁接続部11乞形成する。すなわち画素子
3,4ンできるだけ近接させた状態で、隙間lO内に例
えば樹脂乞注入し硬化させた後フィルム9ン剥離する。
FIG. 2 (ω to (g) are cross-sectional views showing the manufacturing method of a composite semiconductor device according to an embodiment of the present invention in the order of steps, and will be explained below in order of process J. ◎ Step [A]: The steps in FIG. 2(a) A film 9 is prepared on a support base 8, and a desired circuit element is provided on this film 9, and a cylindrical element 3 having an electrode 5 and an elastic surface element 4 made of a piezoelectric substrate are connected with a gap lO. The insulating connection part 11 is formed in the gap 10. That is, with the pixel elements 3 and 4 as close as possible, for example, a resin is injected into the gap 10 and cured, and then the film 9 is peeled off. .

これによって絶縁接続部11を介して各々表面が同一高
さとなるように配置された半導体素子3と弾性表面V素
子4とから成る一体化構造12が得られる。
As a result, an integrated structure 12 consisting of the semiconductor element 3 and the elastic surface V element 4 which are arranged via the insulating connection part 11 so that their surfaces are at the same height is obtained.

工程〔8〕:第2図(b)のように、上記一体化構造1
2の裏面χ接着材13’4介して支持基板l上に固定す
る。次に半導体素子3の電極5の一部χ残してその表面
7周知のフォトリソグラフィー法により例えばポジ型レ
ジストから成る第1のレジスト14でもって優う。
Step [8]: As shown in FIG. 2(b), the above integrated structure 1
The back surface χ of No. 2 is fixed onto the support substrate l via the adhesive 13'4. Next, a portion χ of the electrode 5 of the semiconductor element 3 is left and its surface 7 is coated with a first resist 14 made of, for example, a positive type resist by a well-known photolithography method.

工程〔C〕:第2図(c)のように、上記第1のレジス
ト14を含む一体化構造12の表面に蒸着法、スパッタ
法等によってアルミニウム等の金属薄/1115g堆積
させる。この場合半導体素子3の電極5の厚さに比べ上
記第1のレジスト14の厚さの方がかなり大きいので、
この段部に堆積される金属薄膜15の厚さは他よりも小
さくなる。
Step [C]: As shown in FIG. 2(c), 1115 g of a thin metal such as aluminum is deposited on the surface of the integrated structure 12 including the first resist 14 by vapor deposition, sputtering, or the like. In this case, since the thickness of the first resist 14 is considerably larger than the thickness of the electrode 5 of the semiconductor element 3,
The thickness of the metal thin film 15 deposited on this stepped portion is smaller than on the other portions.

工程〔D〕:第2図(d)のように、周知のリフトオフ
法により上記第1のレジスト14と共にこの上の金属薄
[15ン除去する。金属薄膜15は電極5の一部と弾性
表面波素子4との表面に跨るようにして残っている。
Step [D]: As shown in FIG. 2(d), the first resist 14 and the overlying metal thin layer [15 mm] are removed by a well-known lift-off method. The metal thin film 15 remains so as to straddle a part of the electrode 5 and the surfaces of the surface acoustic wave element 4.

工程[E):第2図(e)のように、再びフォトリソグ
ラフィー法により残っている金属薄膜15および電極5
表面の所望部を第2のレジスト16でもって覆う。
Step [E): As shown in FIG. 2(e), the remaining metal thin film 15 and electrode 5 are removed by photolithography again.
A desired portion of the surface is covered with a second resist 16.

第2図げ)に上面図で示すよう[第2のレジスト16で
覆われる所望部は、半導体素子3の′BL他5およびこ
の電極5から延長された金属薄膜巧の部分である。
As shown in the top view in FIG. 2, the desired portions to be covered with the second resist 16 are the semiconductor element 3 and the metal thin film layer extending from the electrode 5.

工程〔F〕:第2図(glのように、上記第2のレジス
ト16ヲマスクとして金属薄膜15i選択的にエツチン
グする。第2のレジスト16 g除去すること忙より、
半導体素子3の1!極5と弾性表面波素子4との表面に
跨り瓦配腺17が得られる。
Step [F]: As shown in FIG. 2 (gl), the second resist 16 is used as a mask to selectively etch the metal thin film 15i.
Semiconductor element 1 of 3! A tile distribution gland 17 is obtained spanning the surfaces of the pole 5 and the surface acoustic wave element 4.

この時同時に弾性表面波素子4の表面においてはすだれ
状電極6を形成することができる。
At this time, interdigital electrodes 6 can be formed on the surface of the surface acoustic wave element 4 at the same time.

このようにフォトリソグラフィー法を利用して画素子に
跨った配置1iIye形成するようにすれば、その配線
の幅寸法はフオ) IJソゲラフイー法の加工精度によ
って決定され、約1μ程度の幅のものが得られるので、
すだれ状電極と配lfsヲ同時に形成することが可能と
なる。
If the photolithography method is used to form an arrangement 1iIye spanning the pixel elements, the width of the wiring will be determined by the processing accuracy of the IJ Sogelafy method, and the width of the wiring will be approximately 1μ. Because you can get
It becomes possible to form the interdigital electrodes and the electrodes at the same time.

フォトリソグラフィー法で用いられるレジストのa類は
ポジ型に限らずネガ型も同様に用いることができる。
The type a resists used in photolithography are not limited to positive types, but negative types can be used as well.

また機能素子としても弾性表面波素子に限ることはない
Further, the functional element is not limited to a surface acoustic wave element.

以上説明して明らかなように本発明によれば、半導体素
子と機能素子とを各々表面が同一高さとなるように絶縁
物を介して一体化構造となし、画素子表面に金属薄膜?
形成した後フォトリングラフイー法Z利用して画素子表
面に跨がる微細幅の配線を形成するように構成したもの
であるから、従来のように特殊な工程を用いないでも複
合中導体装置を容易に製造することができる。
As is clear from the above description, according to the present invention, a semiconductor element and a functional element are integrated with each other via an insulator so that their surfaces are at the same height, and a metal thin film is formed on the surface of the pixel element.
After formation, the structure is such that a fine-width wiring that spans the pixel surface is formed using the photophosphorography method Z, so it is possible to create a composite medium conductor device without using special processes as in the past. can be easily manufactured.

よってコストダウンを計ることができ、また画素子表面
に跨って接続される配線のオーミック性乞改善すること
ができるので優れた性能の複合半導体装tv得ることが
できる。
Therefore, it is possible to reduce the cost and improve the ohmic characteristics of the wiring connected across the surface of the pixel element, so that a composite semiconductor device TV with excellent performance can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明を説明するための斜視図、第2図(a)
乃至(―は本発明実施例〉工程順に示す断面図および上
面図である。 l・・・支持基板、3・・・半導体素子、4・・・弾性
表面波素子(機能素子)、5,6・・・を極、8・・・
支持台、9・・・フィルム、10・・・隙間、11・・
・絶縁接続部、臣・・・一体化構造、13・・・接着材
、14.16・・・レジスト、15・・・金属薄膜、1
6・・・配線。 第1図 第2図 第2図
Fig. 1 is a perspective view for explaining the present invention, Fig. 2(a)
to (- are examples of the present invention) are cross-sectional views and top views shown in the order of steps. 1...Support substrate, 3...Semiconductor element, 4...Surface acoustic wave element (functional element), 5, 6 ...is pole, 8...
Support stand, 9... Film, 10... Gap, 11...
・Insulating connection part, member...integrated structure, 13...adhesive, 14.16...resist, 15...metal thin film, 1
6...Wiring. Figure 1 Figure 2 Figure 2

Claims (1)

【特許請求の範囲】 1、(A)半導体素子と機能素子とを各々表面が同一高
さとなるように絶縁物を介して一体化する工程、 (B)一体化構造における半導体素子表面の所望部を覆
うように第1のレジストを形成する工程、 (C)第1のレジストを含む一体化構造表面に金属薄膜
を形成する工程、 (D)第1のレジストと共に金属薄膜の一部を除去する
工程、 (E)残りの金属薄膜および半導体素子表面の所望部を
覆うように第2のレジストを形成する工程、 (F)第2のレジストをマスクとして金属薄膜を選択的
に除去することにより半導体素子と機能素子との各々表
面に跨つた配線を形成する工程、を含むことを特徴とす
る複合半導体装置の製造方法。 2、上記(B)工程が一体化構造における半導体素子の
電極表面を一部を残して覆うように第1のレジストを形
成する工程から成り、上記(F)工程が第2のレジスト
をマスクとして金属薄膜を選択的に除去することにより
半導体素子の電極表面の一部と機能素子との各々表面に
跨つた配線を形成する工程から成ることを特徴とする特
許請求の範囲第1項記載の複合半導体装置の製造方法。 3、上記機能素子が弾性表面波素子から成ることを特徴
とする特許請求の範囲第1項又は第2項記載の複合半導
体装置の製造方法。
[Claims] 1. (A) A step of integrating a semiconductor element and a functional element via an insulator so that their surfaces are at the same height; (B) A desired portion of the surface of the semiconductor element in the integrated structure. (C) forming a metal thin film on the surface of the integrated structure including the first resist; (D) removing a part of the metal thin film together with the first resist; (E) forming a second resist so as to cover the remaining metal thin film and a desired portion of the surface of the semiconductor element; (F) selectively removing the metal thin film using the second resist as a mask; 1. A method for manufacturing a composite semiconductor device, comprising the step of forming wiring spanning the surfaces of an element and a functional element. 2. The above step (B) consists of a step of forming a first resist so as to cover all but a portion of the electrode surface of the semiconductor element in the integrated structure, and the above step (F) consists of forming a first resist using the second resist as a mask. The composite according to claim 1, comprising the step of selectively removing a metal thin film to form a wiring that spans a part of the electrode surface of the semiconductor element and the surface of the functional element. A method for manufacturing a semiconductor device. 3. The method for manufacturing a composite semiconductor device according to claim 1 or 2, wherein the functional element is a surface acoustic wave element.
JP16507184A 1984-08-06 1984-08-06 Manufacture of complex semiconductor device Pending JPS6142943A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16507184A JPS6142943A (en) 1984-08-06 1984-08-06 Manufacture of complex semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16507184A JPS6142943A (en) 1984-08-06 1984-08-06 Manufacture of complex semiconductor device

Publications (1)

Publication Number Publication Date
JPS6142943A true JPS6142943A (en) 1986-03-01

Family

ID=15805314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16507184A Pending JPS6142943A (en) 1984-08-06 1984-08-06 Manufacture of complex semiconductor device

Country Status (1)

Country Link
JP (1) JPS6142943A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04342308A (en) * 1991-05-20 1992-11-27 Murata Mfg Co Ltd Piezoelectric resonator
US6075307A (en) * 1997-01-31 2000-06-13 Nec Corporation Surface acoustic wave system
JP2001274315A (en) * 2000-03-24 2001-10-05 Sony Corp Semiconductor device and its manufacturing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56115553A (en) * 1980-02-18 1981-09-10 Fujitsu Ltd Method of mounting integrated circuit
JPS58184753A (en) * 1982-04-23 1983-10-28 Clarion Co Ltd Composite semiconductor device
JPS5940553A (en) * 1982-08-30 1984-03-06 Hitachi Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56115553A (en) * 1980-02-18 1981-09-10 Fujitsu Ltd Method of mounting integrated circuit
JPS58184753A (en) * 1982-04-23 1983-10-28 Clarion Co Ltd Composite semiconductor device
JPS5940553A (en) * 1982-08-30 1984-03-06 Hitachi Ltd Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04342308A (en) * 1991-05-20 1992-11-27 Murata Mfg Co Ltd Piezoelectric resonator
US6075307A (en) * 1997-01-31 2000-06-13 Nec Corporation Surface acoustic wave system
JP2001274315A (en) * 2000-03-24 2001-10-05 Sony Corp Semiconductor device and its manufacturing method

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