JPS5530825A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5530825A
JPS5530825A JP10354078A JP10354078A JPS5530825A JP S5530825 A JPS5530825 A JP S5530825A JP 10354078 A JP10354078 A JP 10354078A JP 10354078 A JP10354078 A JP 10354078A JP S5530825 A JPS5530825 A JP S5530825A
Authority
JP
Japan
Prior art keywords
bump
polysilicon
grown
photoetching
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10354078A
Other languages
Japanese (ja)
Inventor
Yoichi Iga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP10354078A priority Critical patent/JPS5530825A/en
Publication of JPS5530825A publication Critical patent/JPS5530825A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To reduce material cost and device cost by forming a bump terminal in such a way that it may include the upmost metallic layer and a semiconductor layer under the former.
CONSTITUTION: A metallic electrode is provided on the surface of a semiconductor substrate by an Al vapor depositing method, a photoetching method, etc., and on the metallic electrode, a semiconductor layer, for example, polysilicon in grown by a CVD method only in the region where a bump will be formed afterwards by plating gold, and a bump is formed on the polsilicon by a gold plating method. For example, after Al is vapor deposited on the surface of a silicon monocrystalline substrate 101 and a metallic electrode 102 is made by photoetching, an oxide film 105 is grown and an opening is made by photoetching. Next, polysilicon is grown by the CVD method and polysilicon 107 is provided in the region which will become a bump. Next, after forming an Al layer and a photoresist layer, making the opening on the polysilicon and providing a bump 111 by plating gold, the photoresist and the Al layers are removed. By so doing, a bump whose material cost and device cost are cheaper than titanium platinum can be obtained.
COPYRIGHT: (C)1980,JPO&Japio
JP10354078A 1978-08-24 1978-08-24 Semiconductor device Pending JPS5530825A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10354078A JPS5530825A (en) 1978-08-24 1978-08-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10354078A JPS5530825A (en) 1978-08-24 1978-08-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5530825A true JPS5530825A (en) 1980-03-04

Family

ID=14356667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10354078A Pending JPS5530825A (en) 1978-08-24 1978-08-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5530825A (en)

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